Erich Barke

Stefan Hoelldampf, H.-S. L. Lee, Daniel Zaum, Markus Olbrich, Erich Barke: Efficient generation of analog circuit models for accelerated mixed-signal simulation. SoCC 2012: 104-109

Artur Quiring, Marc Lindenberg, Markus Olbrich, Erich Barke: 3D floorplanning considering vertically aligned rectilinear modules using T^∗-tree. 3DIC 2011: 1-5

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz: A theoretical probabilistic simulation framework for dynamic power estimation. ICCAD 2011: 708-715

Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke: Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation. ICCD 2011: 108-112

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz: A gate sizing method for glitch power reduction. SoCC 2011: 24-29

M. Zhang, R. Haussler, Markus Olbrich, Harald Kinzelbach, Erich Barke: A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization. VLSI Design 2011: 106-111

Florian Schupfer, Christoph Grimm, Markus Olbrich, Michael Kärgel, Erich Barke: Towards Abstract Analysis Techniques for Range Based System Simulations. FDL 2010: 159-164

Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann: An Accelerated Mixed-Signal Simulation Kernel for SystemC. FDL 2010: 234-239

Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang: Formal approaches to analog circuit verification. DATE 2009: 724-729

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler: Fast dynamic power estimation considering glitch filtering. SoCC 2009: 361-364

Markus Olbrich, Erich Barke: Distribution arithmetic for stochastical analysis. ASP-DAC 2008: 537-542

Darius Grabowski, Markus Olbrich, Erich Barke: Analog circuit simulation using range arithmetics. ASP-DAC 2008: 762-767

Peter Leppelt, Erich Barke: Determining the Technical Complexity of Integrated Circuits. DATE 2008: 935

Thomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke: A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. DDECS 2008: 54-58

Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt: Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). FDL 2008: 73-77

Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl: Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI 2008: 17-22

Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke: Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. DAC 2007: 706-711

M. Zhang, Markus Olbrich, D. Seider, M. Frerichs, Harald Kinzelbach, Erich Barke: CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. DATE 2007: 243-248

Darius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke: Range Arithmetics to Speed up Reachability Analysis of Analog Systems. FDL 2007: 38-43

Jan Torben Weinkopf, Klaus Harbich, Erich Barke: Incremental Fault Emulation. FPL 2007: 542-545

Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl: Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI 2007: 43-48

Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten: Algorithms for automatic length compensation of busses in analog integrated circuits. ISPD 2007: 159-166

Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke: Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. Electr. Notes Theor. Comput. Sci. 153(3): 37-52 (2006)

Daniel Platte, Shangjing Jing, Ralf Sommer, Erich Barke: Using Sequential Equations to Improve Efficiency and Robustness. FDL 2006: 83-90

Jan Torben Weinkopf, Klaus Harbich, Erich Barke: Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. FPL 2006: 1-6

Darius Grabowski, Christoph Grimm, Erich Barke: Semi-symbolic modeling and simulation of circuits and systems. ISCAS 2006

Ralf Klausen, Lars Hedrich, Erich Barke: Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen. MBMV 2006: 122-131

Darius Grabowski, Christoph Grimm, Erich Barke: Ein Verfahren zur effizienten Analyse von Schaltungen mit Parametervarianzen. MBMV 2006: 181-190

Daniel Platte, Shangjing Jing, Ralf Sommer, Erich Barke: Ansätze zur Verbesserung der Simulationsperformance automatisch generierter analoger Verhaltensmodelle. MBMV 2006: 191-200

Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten: Routing of analog busses with parasitic symmetry. ISPD 2005: 14-19

Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke: Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. DATE 2004: 442-447

Markus Olbrich, Erich Barke: Placement Using a Localization Probability Model (LPM). DATE 2004: 1412

Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke: Wirelength Reduction Using 3-D Physical Design. PATMOS 2004: 453-462

Andreas Hermann, Markus Olbrich, Erich Barke: Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. VLSI-SOC 2003: 13-18

Walter Hartong, Lars Hedrich, Erich Barke: On Discrete Modeling and Model Checking for Nonlinear Analog Systems. CAV 2002: 401-413

Walter Hartong, Lars Hedrich, Erich Barke: Model checking algorithms for analog verification. DAC 2002: 542-547

Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke: Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. DATE 2002: 274-278

Walter Hartong, Lars Hedrich, Erich Barke: An Approach to Model Checking for Nonlinear Analog Systems. DATE 2002: 1080

Joerg Abke, Erich Barke: A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . DATE 2002: 1085

Andreas C. Lemke, Lars Hedrich, Erich Barke: Analog circuit sizing based on formal methods using affine arithmetic. ICCAD 2002: 486-489

Silke Salewski, Erich Barke: An Upper Bound for 3D Slicing Floorplans. VLSI Design 2002: 567-572

Joachim Küter, Erich Barke: Architecture driven partitioning. DATE 2001: 479-487

Markus Olbrich, Achim Rein, Erich Barke: An improved hierarchical classification algorithm for structural analysis of integrated circuits. DATE 2001: 807

Joerg Abke, Erich Barke: A New Placement Method for Direct Mapping into LUT-Based FPGAs. FPL 2001: 27-36

Klaus Harbich, Erich Barke: PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. FPL 2001: 133-141

Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch: CHIPDESIGN - A Novel Project-oriented Microelectronics Course. MSE 2001: 71-72

Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke: A current driven routing and verification methodology for analog applications. DAC 2000: 385-389

Thorsten Adler, Erich Barke: Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. DATE 2000: 446-450

Matthias Ringe, Thomas Lindenkreuz, Erich Barke: Static Timing Analysis Taking Crosstalk into Account. DATE 2000: 451-455

Joerg Abke, Erich Barke: CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. FPL 2000: 191-200

Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel: PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. PATMOS 2000: 306-315

Dimitrios Soudris, Peter Pirsch, Erich Barke (Eds.): Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings. Lecture Notes in Computer Science 1918, Springer 2000, isbn 3-540-41068-6

Klaus Harbich, Jörn Stohmann, Erich Barke, Ludwig Schwoerer: A Case Study: Logic Emulation - Pitfalls and Solutions. IEEE International Workshop on Rapid System Prototyping 1999: 160-

Joerg Abke, Erich Barke, Jörn Stohmann: A Universal Module Generator for LUT-Based FPGAs. IEEE International Workshop on Rapid System Prototyping 1999: 230-235

Reza Sedaghat-Maman, Erich Barke: Real Time Fault Injection Using Logic Emulators. ASP-DAC 1998: 475-479

Lars Hedrich, Erich Barke: A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. DATE 1998: 649-654

Matthias Ringe, Thomas Lindenkreuz, Erich Barke: Path Verification Using Boolean Satisfiability. DATE 1998: 965-966

Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke: An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. FPL 1998: 79-88

Dirk Behrens, Erich Barke, Robert Tolkiehn: Design driven partitioning. ASP-DAC 1997: 49-55

Jörn Stohmann, Erich Barke: A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. ICCD 1997: 489-495

Reza Sedaghat-Maman, Erich Barke: A new approach to fault emulation. IEEE International Workshop on Rapid System Prototyping 1997: 173-179

Carsten Borchers, Lars Hedrich, Erich Barke: Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. DAC 1996: 236-239

Jörn Stohmann, Erich Barke: A Universal CLA Adder Generator for SRAM-Based FPGAs. FPL 1996: 44-54

Dirk Behrens, Klaus Harbich, Erich Barke: Hierarchical partitioning. ICCAD 1996: 470-477

Lars Hedrich, Erich Barke: A formal approach to nonlinear analog circuit verification. ICCAD 1995: 123-127

Erich Barke: Line-to-ground capacitance calculation for VLSI: a comparison. IEEE Trans. on CAD of Integrated Circuits and Systems 7(2): 295-298 (1988)

Erich Barke: FERKEL: Technologieunabhängiges direktivengesteuertes Programmsystem zur Entwurfsregelnprüfung. Angewandte Informatik 27(8): 328-333 (1985)

Erich Barke: Resistance calculation from mask artwork data by finite element method. DAC 1985: 305-311

F. Luellau, T. Hoepken, Erich Barke: A technology independent block extraction algorithm. DAC 1984: 610-615

Erich Barke: A layout verification system for analog bipolar integrated circuits. DAC 1983: 353-359