Edna Barros

Rodolfo P. dos Santos, Gabriela S. Clemente, Abel Guilhermino Silva-Filho, Cristiano C. de Araujo, Sarmento Adriano, Manoel Eusebio de Lima, Edna Barros: An Optimization Mechanism Intended for Static Power Reduction Using Dual-VthTechnique. J. Electrical and Computer Engineering 2012 (2012)

Thiago Cardoso, Edna Barros, Bruno Prado, Andre Aziz: Communication software synthesis from UML-ESL models. SBCCI 2012: 1-6

Abel Guilhermino Silva-Filho, Filipe R. Cordeiro, Cristiano C. de Araujo, Sarmento Adriano, Millena Gomes, Edna Barros, Manoel Eusebio de Lima: An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms. Int. J. Reconfig. Comp. 2011 (2011)

Bruno Prado, Edna Barros, Thiago Figueiredo, Andre Aziz: HdSC: a fast and preemptive modeling for on host HdS development. SBCCI 2011: 179-184

Diogo José Costa Alves, Edna Barros: A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns. SBCCI 2009

Edson Lisboa, Luciano Silva, Igino Chaves, Thiago Lima, Edna Barros: A design flow based on a domain specific language to concurrent development of device drivers and device controller simulation models. SCOPES 2009: 53-60

Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid: A table-based method for single-pass cache optimization. ACM Great Lakes Symposium on VLSI 2008: 71-76

Bruno Albertini, Sandro Rigo, Guido Araujo, Cristiano C. de Araujo, Edna Barros, Willians Azevedo: A computational reflection mechanism to support platform debugging in SystemC. CODES+ISSS 2007: 81-86

Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros: A one-shot configurable-cache tuner for improved energy and performance. DATE 2007: 755-760

Andre Silva, Guilherme Esmeraldo, Edna Barros, Pablo Viana: Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass. IEEE International Workshop on Rapid System Prototyping 2007: 3-9

Jordana L. Seixas, Edson Barbosa, Stelita M. da Silva, Paulo Sérgio B. do Nascimento, Vinícius Kursancew, Remy Eskinazi Sant'Anna, Edna Barros, Manoel Eusebio de Lima: Aquarius: a dynamically reconfigurable computing platform. SBCCI 2007: 171-176

Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid: Configurable cache subsetting for fast cache tuning. DAC 2006: 695-700

Abel Guilhermino Silva-Filho, Pablo Viana, Edna Barros, Manoel Eusebio de Lima: Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption. SBAC-PAD 2006: 125-132

Guido Araujo, Edna Barros, Elmar U. K. Melcher, Rodolfo Azevedo, Karina R. G. da Silva, Bruno Prado, Manoel Eusebio de Lima: A SystemC-only design methodology and the CINE-IP multimedia platform. Design Autom. for Emb. Sys. 10(2-3): 181-202 (2005)

Cristiano C. de Araujo, Millena Gomes, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo: Platform designer: An approach for modeling multiprocessor platforms based on SystemC. Design Autom. for Emb. Sys. 10(4): 253-283 (2005)

Rodolfo Azevedo, Sandro Rigo, Marcus Bartholomeu, Guido Araujo, Cristiano C. de Araujo, Edna Barros: The ArchC Architecture Description Language and Tools. International Journal of Parallel Programming 33(5): 453-484 (2005)

Danielly Cruz, Edna Barros: Vital Signs Remote Management System for PDAs. DSD 2005: 170-175

Cristiano C. de Araujo, Edna Barros, Rodolfo Azevedo, Guido Araujo: Processor Centric Specification and Modelling of MPSoCs. FDL 2005: 303-315

Marilia Lima, F. Santos, J. Bione, T. Lins, Edna Barros: IpPROCESS: a Development Process for Soft IP-Cord. FDL 2005: 487-499

Marilia Lima, Andre Aziz, Diogo José Costa Alves, Patricia Lira, Vitor Schwambach, Edna Barros: ipPROCESS: Using a Process to Teach IP-Core Development. MSE 2005: 27-28

Leila Silva, Augusto Sampaio, Edna Barros: A Constructive Approach to Hardware/Software Partitioning. Formal Methods in System Design 24(1): 45-90 (2004)

Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo: Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. DATE 2004: 734-735

Albano Portela Machado, Paulo Romero Martins Maciel, Edna Barros: A Petri net based method for functional and interconnect units estimation. SMC (5) 2004: 4983-4988

Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo: Exploring Memory Hierarchy with ArchC. SBAC-PAD 2003: 2-9

Cristiano C. de Araujo, Edna Barros: Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design. VLSI-SOC 2001: 145-156

Paulo Romero Martins Maciel, Edna Barros, Wolfgang Rosenstiel: A Petri Net Model for Hardware/Software Codesign. Design Autom. for Emb. Sys. 4(4): 243-310 (1999)

Leila Silva, Augusto Sampaio, Edna Barros, Juliano Iyoda: An Algebraic Approach to Combining Processes in a Hardware/Software Partitioning Environment. AMAST 1998: 308-324

Cristiano C. de Araujo, Marcus V. D. dos Santos, Edna Barros: A FPGA-based Implementation of an Intravenous Infusion Controller System. ASAP 1997: 402-411

Leila Silva, Augusto Sampaio, Edna Barros: A Normal Form Reduction Strategy for Hardware/Software Partitioning. FME 1997: 624-643

Paulo Romero Martins Maciel, Edna Barros, Wolfgang Rosenstiel: Computing communication cost by Petri nets for hardware/software codesign. IEEE International Workshop on Rapid System Prototyping 1997: 44-56

Edna Barros, Augusto Sampaio: Towards provably correct hardware/software partitioning using occam. CODES 1994: 210-217

Xun Xiong, Edna Barros, Wolfgang Rosenstiel: A method for partitioning UNITY language in hardware and software. EURO-DAC 1994: 220-225