| 1988 | ||
|---|---|---|
| j5 | Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman: SLS-a fast switch-level simulator [for MOS]. IEEE Trans. on CAD of Integrated Circuits and Systems 7(8): 838-849 (1988) | |
| 1987 | ||
| j4 | Zeev Barzilai, J. Lawrence Carter, Barry K. Rosen, Joe D. Rutledge: HSS--A High-Speed Simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 6(4): 601-617 (1987) | |
| 1986 | ||
| c6 | Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman: SLS - a fast switch level simulator for verification and fault coverage analysis. DAC 1986: 164-170 | |
| c5 | Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman: Efficient Fault Simulation of CMOS Circuits with Accurate Models. ITC 1986: 520-529 | |
| 1985 | ||
| c4 | Zeev Barzilai, Vijay S. Iyengar, Barry K. Rosen, Gabriel M. Silberman: Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits. ITC 1985: 722-731 | |
| 1984 | ||
| j3 | Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman: Using a Hardware Simulation Engine for Custom MOS Structured Designs. IBM Journal of Research and Development 28(5): 564-571 (1984) | |
| 1983 | ||
| j2 | Zeev Barzilai, Don Coppersmith, Arnold L. Rosenberg: Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing. IEEE Trans. Computers 32(2): 190-194 (1983) | |
| c3 | Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo: Simulating pass transistor circuits using logic simulation machines. DAC 1983: 157-163 | |
| c2 | ||
| 1981 | ||
| j1 | Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith: The Weighted Syndrome Sums Approach to VLSI Testing. IEEE Trans. Computers 30(12): 996-1000 (1981) | |
| c1 | Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith: VLSI Self-Testing Based on Syndrome Techniques. ITC 1981: 102-109 | |
Colors in the list of coauthors
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