Kia Bazargan

Peng Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja: The synthesis of linear Finite State Machine-based Stochastic Computational Elements. ASP-DAC 2012: 757-762

Weikang Qian, Chen Wang, Peng Li, David J. Lilja, Kia Bazargan, Marc D. Riedel: An efficient implementation of numerical integration using logical computation on stochastic bit streams. ICCAD 2012: 156-162

Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel: The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic. ICCAD 2012: 480-487

Peng Li, Weikang Qian, David J. Lilja, Kia Bazargan, Marc D. Riedel: Case Studies of Logical Computation on Stochastic Bit Streams. PATMOS 2012: 235-244

Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, David J. Lilja: An Architecture for Fault-Tolerant Computation with Stochastic Logic. IEEE Trans. Computers 60(1): 93-105 (2011)

Hossein Omidian Savarbaghi, Kia Bazargan: FPGA placement by graph isomorphism (abstract only). FPGA 2011: 284

Pongstorn Maidee, Kia Bazargan: Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1870-1883 (2010)

Pongstorn Maidee, Kia Bazargan: A fast SPFD-based rewiring technique. ASP-DAC 2010: 55-60

Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan: Fast and Accurate Statistical Criticality Computation Under Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 350-363 (2009)

Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan: A tileable switch module architecture for homogeneous 3D FPGAs. 3DIC 2009: 1-4

Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Ardestani, Gholamhossein Tavasoli, Kia Bazargan: Using randomization to cope with circuit uncertainty. DATE 2009: 815-820

Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja: A reconfigurable stochastic architecture for highly reliable computing. ACM Great Lakes Symposium on VLSI 2009: 315-320

Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja: The synthesis of combinational logic to generate probabilities. ICCAD 2009: 367-374

Satish Sivaswamy, Kia Bazargan, Marc D. Riedel: Estimation and optimization of reliability of noisy digital circuits. ISQED 2009: 213-219

Satish Sivaswamy, Kia Bazargan: Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs. TRETS 1(1) (2008)

Pongstorn Maidee, Nagib Hakim, Kia Bazargan: FPGA family composition and effects of specialized blocks. FPL 2008: 101-106

Hushrav Mogal, Kia Bazargan: Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. ICCAD 2008: 302-305

Kia Bazargan, André DeHon: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 201-202 (2007)

Hushrav Mogal, Kia Bazargan: Microarchitecture floorplanning for sub-threshold leakage reduction. DATE 2007: 1238-1243

Satish Sivaswamy, Kia Bazargan: Variation-aware routing for FPGAs. FPGA 2007: 71-79

Pongstorn Maidee, Kia Bazargan: A generalized and unified SPFD-based rewiring technique. FPL 2007: 305-310

Satish Sivaswamy, Kia Bazargan: Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs. FPL 2007: 429-434

Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan: Clustering based pruning for statistical criticality computation under process variations. ICCAD 2007: 340-343

Cristinel Ababei, Kia Bazargan: Non-contiguous linear placement for reconfigurable fabrics. IJES 2(1/2): 86-94 (2006)

Cristinel Ababei, Hushrav Mogal, Kia Bazargan: Three-dimensional place and route for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1132-1140 (2006)

Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh: Statistical Analysis and Design of HARP FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2088-2102 (2006)

Pongstorn Maidee, Kia Bazargan: Defect-Tolerant FPGA Architecture Exploration. FPL 2006: 1-6

Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar: Placement and Routing in 3D Integrated Circuits. IEEE Design & Test of Computers 22(6): 520-531 (2005)

Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan: A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory. J. Comput. Sci. Technol. 20(5): 596-606 (2005)

Pongstorn Maidee, Cristinel Ababei, Kia Bazargan: Timing-driven partitioning-based placement for island style FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 395-406 (2005)

Cristinel Ababei, Hushrav Mogal, Kia Bazargan: Three-dimensional place and route for FPGAs. ASP-DAC 2005: 773-778

Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh: HARP: hard-wired routing pattern FPGAs. FPGA 2005: 21-29

Cristinel Ababei, Hushrav Mogal, Kia Bazargan: 3D FPGAs: placement, routing, and architecture evaluation (abstract only). FPGA 2005: 263

John Lach, Kia Bazargan: Editorial: Special issue on dynamically adaptable embedded systems. ACM Trans. Embedded Comput. Syst. 3(2): 233-236 (2004)

Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan: Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory. Asia-Pacific Computer Systems Architecture Conference 2004: 88-101

Cristinel Ababei, Pongstorn Maidee, Kia Bazargan: Exploring Potential Benefits of 3D FPGA Integration. FPL 2004: 874-880

Cristinel Ababei, Kia Bazargan: Non-Contiguous Linear Placement for Reconfigurable Fabrics. IPDPS 2004

Pongstorn Maidee, Cristinel Ababei, Kia Bazargan: Fast timing-driven partitioning-based placement for island style FPGAs. DAC 2003: 598-603

Wonjoon Choi, Kia Bazargan: Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration. DATE 2003: 11104-11105

Karthikeyan Bhasyam, Kia Bazargan: HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. DSD 2003: 264-271

Vamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan: Linear Placement for Static / Dynamic Reconfiguration in JBits. FCCM 2003: 300-301

Cristinel Ababei, Kia Bazargan: Placement Method Targeting Predictability Robustness and Performance. ICCAD 2003: 81-85

Wonjoon Choi, Kia Bazargan: Incremental Placement for Timing Optimization. ICCAD 2003: 463-466

Cristinel Ababei, Kia Bazargan: Timing Minimization by Statistical Timing hMetis-based Partitioning. VLSI Design 2003: 58-63

Jinghuan Chen, Jaekyun Moon, Kia Bazargan: A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator. DAC 2002: 349-354

Cristinel Ababei, Kia Bazargan: Statistical Timing Driven Partitioning for VLSI Circuits. DATE 2002: 1109

Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis: Multi-objective circuit partitioning for cutsize and path-based delay minimization. ICCAD 2002: 181-185

Abhishek Ranjan, Kia Bazargan, S. Ogrenci, Majid Sarrafzadeh: Fast floorplanning for effective prediction and construction. IEEE Trans. VLSI Syst. 9(2): 341-351 (2001)

Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh: Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. DAC 2001: 635-640

Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh: 3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. Design Autom. for Emb. Sys. 5(3-4): 329-338 (2000)

Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh: Fast Template Placement for Reconfigurable Computing Systems. IEEE Design & Test of Computers 17(1): 68-83 (2000)

Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh: A C to Hardware/Software Compiler. FCCM 2000: 331-332

Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh: Fast and accurate estimation of floorplans in logic/high-level synthesis. ACM Great Lakes Symposium on VLSI 2000: 95-100

Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh: Fast Hierarchical Floorplanning with Congestion and Timing Control. ICCD 2000: 357-362

Kia Bazargan, Samjung Kim, Majid Sarrafzadeh: Nostradamus: a floorplanner of uncertain designs. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 389-397 (1999)

Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh: 3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. IEEE International Workshop on Rapid System Prototyping 1999: 38-

Kia Bazargan, Samjung Kim, Majid Sarrafzadeh: Nostradamus: a floorplanner of uncertain design. ISPD 1998: 18-23