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Valeriu Beiu
2010 – today
- 2013
[c39]Valeriu Beiu, Azam Beg, Walid Ibrahim, Fekri Kharbash, Massimo Alioto: Enabling sizing for enhancing the static noise margins. ISQED 2013: 278-285- 2012
- [j10]Walid Ibrahim, Valeriu Beiu, Azam Beg: GREDA: A Fast and More Accurate Gate Reliability EDA Tool. IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 509-521 (2012)
- [j9]Walid Ibrahim, Valeriu Beiu, Azam Beg: Optimum Reliability Sizing for Complementary Metal Oxide Semiconductor Gates. IEEE Transactions on Reliability 61(3): 675-686 (2012)
- 2011
- [j8]Valeriu Beiu, Basheer A. M. Madappuram, Peter M. Kelly, Liam McDaid: On Two-Layer Brain-Inspired Hierarchical Topologies - A Rent's Rule Approach -. T. HiPEAC 4: 311-333 (2011)
- [j7]Walid Ibrahim, Valeriu Beiu: Using Bayesian Networks to Accurately Calculate the Reliability of Complementary Metal Oxide Semiconductor Gates. IEEE Transactions on Reliability 60(3): 538-549 (2011)
- [c38]Valeriu Beiu, Walid Ibrahim, Azam Beg, Liren Zhang, Mihai Tache: On axon-inspired communications. ECCTD 2011: 789-792
- [c37]John J. Wade, Liam McDaid, Jim Harkin, Vincenzo Crunelli, J. A. Scott Kelso, Valeriu Beiu: Exploring retrograde signaling via astrocytes as a mechanism for self repair. IJCNN 2011: 3149-3155
- 2010
- [c36]Liren Zhang, Hesham El-Sayed, Valeriu Beiu: A Position-Based Broadcast Relay Approach in Mobile Vehicle-to-Vehicle Network. ICWN 2010: 611-616
2000 – 2009
- 2009
- [c35]Valeriu Beiu, Basheer A. M. Madappuram, Peter M. Kelly, Liam McDaid: On Two-Layer Hierarchical Networks How Does the Brain Do This? NanoNet 2009: 231-241
- [c34]Peter M. Kelly, Fergal Tuffy, Valeriu Beiu, Liam McDaid: Reduced Interconnects in Neural Networks Using a Time Multiplexed Architecture Based on Quantum Devices. NanoNet 2009: 242-250
- [c33]Valeriu Beiu, Walid Ibrahim, Rafic Z. Makki: On Wires Holding a Handful of Electrons. NanoNet 2009: 259-269
- [c32]Walid Ibrahim, Valeriu Beiu: A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations. NanoNet 2009: 276-284
- [e1]Alexandre Schmid, Sanjay Goel, Wei Wang, Valeriu Beiu, Sandro Carrara (Eds.): Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering 20, Springer 2009, ISBN 978-3-642-04849-4
- [r1]Valeriu Beiu, Walid Ibrahim, Sanja Lazarova-Molnar: Device-Level Majority von Neumann Multiplexing. Encyclopedia of Artificial Intelligence 2009: 471-479
- 2008
- [c31]
- [c30]Valeriu Beiu, Basheer A. M. Madappuram, T. Martin McGinnity: On brain-inspired hybrid topologies for nano-architectures - a Rent's rule approach -. ICSAMOS 2008: 33-40
- 2007
- [c29]Walid Ibrahim, Valeriu Beiu: Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming! ASAP 2007: 278-283
- [c28]Valeriu Beiu: Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore. ISMVL 2007
- [c27]Valeriu Beiu, Walid Ibrahim, Sanja Lazarova-Molnar: What von Neumann Did Not Say About Multiplexing Beyond Gate Failures - The Gory Details. IWANN 2007: 487-496
- 2006
- [c26]Valeriu Beiu, Jabulani Nyathi, Snorre Aunet, Mawahib H. Sulieman: Femto Joule Switching for Nano Electronics. AICCSA 2006: 415-423
- [c25]Mawahib H. Sulieman, Valeriu Beiu: Multiplexing Schemes in Single-Electron Technology. AICCSA 2006: 424-428
- [c24]Valeriu Beiu, Walid Ibrahim, Y. A. Alkhawwar, Mawahib H. Sulieman: Gate Failures Effectively Shape Multiplexing. DFT 2006: 29-40
- 2005
- [c23]Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal: On the Advantages of Serial Architectures for Low-Power Reliable Computations. ASAP 2005: 276-281
- [c22]Valeriu Beiu, Artur Zawadski, Razvan Andonie, Snorre Aunet: Using Kolmogorov Inspired Gates for Low Power Nanoelectronics. IWANN 2005: 438-445
- [c21]Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet: Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures. IWANN 2005: 486-493
- 2004
- [c20]Valeriu Beiu: A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments. ASAP 2004: 167-177
- [c19]David J. Betowski, Daniel Dwyer, Valeriu Beiu: A Novel Segmented Parabolic Sine Approximation for Direct Digital Frequency Synthesizers. ESA/VLSI 2004: 523-529
- [c18]Valeriu Beiu, Mawahib H. Sulieman: Optimal Practical Perceptron Addition Application to Single Electron Technology. ESA/VLSI 2004: 541-550
- [c17]Mawahib H. Sulieman, Valeriu Beiu: Characterization of a 16-bit threshold logic single-electron technology adder. ISCAS (3) 2004: 681-684
- 2003
- [j6]Valeriu Beiu, José M. Quintana, Maria J. Avedillo: VLSI implementations of threshold logic-a comprehensive survey. IEEE Transactions on Neural Networks 14(5): 1217-1243 (2003)
- [c16]Valeriu Beiu, Maria J. Avedillo, José M. Quintana: Review of Capacitive Threshold Gate Implementations. ICANN 2003: 737-744
- [c15]Valeriu Beiu: Constructive Threshold Logic Addition A Synopsis of the Last Decade. ICANN 2003: 745-752
- [c14]Suryanarayana Tatapudi, Valeriu Beiu: Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL). IWANN (2) 2003: 49-56
- [c13]Valeriu Beiu, José M. Quintana, Maria J. Avedillo: Review of Differential Threshold Gate Implementations. Neural Networks and Computational Intelligence 2003: 44-49
- [c12]Valeriu Beiu: On Existential and Constructive Neural Complexity Results. Neural Networks and Computational Intelligence 2003: 63-72
- [c11]Razvan Andonie, Lucian Sasu, Valeriu Beiu: A Modified Fuzzy ARTMAP Architecture for Incremental Learning Function Approximation. Neural Networks and Computational Intelligence 2003: 124-129
1990 – 1999
- 1999
- [j5]Valeriu Beiu, Sorin Draghici, Thierry de Pauw: A Constructive Approach to Calculating Lower Entropy Bounds. Neural Processing Letters 9(1): 1-12 (1999)
- [c10]
- 1998
- [j4]Valeriu Beiu: On the circuit and VLSI complexity of threshold gate COMPARISON. Neurocomputing 19(1-3): 77-98 (1998)
- [j3]Valeriu Beiu, Hanna E. Makaruk: Deeper Sparsely Nets can be Optimal. Neural Processing Letters 8(3): 201-210 (1998)
- [c9]
- [c8]
- 1997
- [c7]Valeriu Beiu: Enhanced lower entropy bounds with application to constructive learning. EUROMICRO 1997: 541-548
- [c6]Valeriu Beiu, Thierry de Pauw: Tight Bounds on the Size of Neural Networks for Classification Problems. IWANN 1997: 743-752
- [c5]Valeriu Beiu, Sorin Draghici, Hanna E. Makaruk: On limited fan-in optimal neural networks. SBRN 1997: 19-30
- 1996
- [j2]Valeriu Beiu, John G. Taylor: On the Circuit Complexity of Sigmoid Feedforward Neural Networks. Neural Networks 9(7): 1155-1171 (1996)
- 1995
- [c4]Valeriu Beiu, John G. Taylor: Optimal Mapping of Neural Networks onto FPGA's - A New Constructive Algorithm -. IWANN 1995: 822-829
- 1994
- [j1]Valeriu Beiu, J. A. Peperstraete, Joos Vandewalle, Rudy Lauwereins: Closse Approximations of Sigmoid Functions by Sum of Step for VLSI Implementation of Neural Networks. Sci. Ann. Cuza Univ. 3: 5-34 (1994)
- [c3]Valeriu Beiu, J. A. Peperstraete, Joos Vandewalle, Rudy Lauwereins: VLSI complexity reduction by piece-wise approximation of the sigmoid function. ESANN 1994
- 1993
- [c2]Valeriu Beiu, J. A. Peperstraete, Joos Vandewalle, Rudy Lauwereins: Efficient decomposition of comparison and its applications. ESANN 1993
1980 – 1989
- 1988
- [c1]
Coauthor Index
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last updated on 2013-06-11 21:49 CEST by the dblp team