Wendy Belluomini

Jorge Guerra, Himabindu Pucha, Joseph S. Glider, Wendy Belluomini, Raju Rangaswami: Cost Effective Storage using Extent Based Dynamic Tiering. FAST 2011: 273-286

Jorge Guerra, Wendy Belluomini, Joseph S. Glider, Karan Gupta, Himabindu Pucha: Energy proportionality for storage: impact and feasibility. Operating Systems Review 44(1): 35-39 (2010)

Pin Zhou, Binny Gill, Wendy Belluomini, Avani Wildani: GAUL: Gestalt Analysis of Unstructured Logs for Diagnosing Recurring Problems in Large Enterprise Storage Systems. SRDS 2010: 148-159

Eric Rozier, Wendy Belluomini, Veera Deenadhayalan, Jim Hafner, K. K. Rao, Pin Zhou: Evaluating the impact of Undetected Disk Errors in RAID systems. DSN 2009: 83-92

James L. Hafner, Veera Deenadhayalan, Wendy Belluomini, Krishnakumar Rao: Undetected disk errors in RAID arrays. IBM Journal of Research and Development 52(4-5): 413-426 (2008)

Mohammad Banikazemi, Jim Hafner, Wendy Belluomini, K. K. Rao, Dan E. Poff, Bülent Abali: Flipstone: managing storage with fail-in-place and deferred maintenance service models. Operating Systems Review 42(1): 54-62 (2008)

Wendy Belluomini, Damir Jamsek, Andrew K. Martin, Chandler McDowell, Robert K. Montoye, Hung C. Ngo, Jun Sawada: Limited switch dynamic logic circuits for high-speed low-power circuit design. IBM Journal of Research and Development 50(2-3): 277-286 (2006)

Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka: A low latency and low power dynamic Carry Save Adder. ISCAS (2) 2004: 477-480

Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Timed circuit verification using TEL structures. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 129-146 (2001)

Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng: Timed circuits: a new paradigm for high-speed design. ASP-DAC 2001: 335-340

Wendy Belluomini, Chris J. Myers: Timed state space exploration using POSETs. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 501-520 (2000)

Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Verification of Delayed-Reset Domino Circuits Using ATACS. ASYNC 1999: 3-12

Robert A. Thacker, Wendy Belluomini, Chris J. Myers: Timed Circuit Synthesis Using Implicit Methods. VLSI Design 1999: 181-188

Wendy Belluomini, Chris J. Myers: Verification of Timed Systems Using POSETs. CAV 1998: 403-415

Wendy Belluomini, Chris J. Myers: Efficient Timing Analysis Algorithms for Timed State Space Exploration. ASYNC 1997: 88-100