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Mladen Berekovic
2010 – today
- 2013
[c34]Boris Motruk, Jonas Diemer, Rainer Buchty, Mladen Berekovic: Power Monitoring for Mixed-Criticality on a Many-Core Platform. ARCS 2013: 13-24- [e5]Mladen Berekovic, Martin Danek (Eds.): ARCS 2013 - 26th International Conference on Architecture of Computing Systems 2013, Workshop Proceedings, Feburary 19-22, 2013, Prague, Czech Republic. VDE-Verlag 2013, ISBN 978-3-8007-3492-4
- 2012
- [j21]Andy D. Pimentel, Naehyuck Chang, Mladen Berekovic: Introduction to special section ESTIMedia'09. ACM Trans. Embedded Comput. Syst. 11(4): 70 (2012)
- [j20]Mladen Berekovic, Samarjit Chakraborty, Petru Eles, Andy D. Pimentel: Introduction to the Special Section on ESTIMedia'08. ACM Trans. Embedded Comput. Syst. 11(S1): 11 (2012)
- [c33]Boris Motruk, Jonas Diemer, Rainer Buchty, Rolf Ernst, Mladen Berekovic: IDAMC: A Many-Core Platform with Run-Time Monitoring for Mixed-Criticality. HASE 2012: 24-31
- 2011
- [c32]Hayder Al-Khalissi, Mladen Berekovic: Performance of RCCE Broadcast Algorithm in SCC. MARC Symposium 2011: 93-98
- [c31]Matti Bickel, Adrian Knoth, Mladen Berekovic: Evaluation of Interpreted Languages with Open MPI. EuroMPI 2011: 292-301
- [e4]Mladen Berekovic, William Fornaciari, Uwe Brinkschulte, Cristina Silvano (Eds.): Architecture of Computing Systems - ARCS 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings. Lecture Notes in Computer Science 6566, Springer 2011, ISBN 978-3-642-19136-7
- 2010
- [j19]
- [j18]Matthias Hartmann, Vasileios (Vassilis) Pantazis, Tom Vander Aa, Mladen Berekovic, Christian Hochberger: Still Image Processing on Coarse-Grained Reconfigurable Array Architectures. Signal Processing Systems 60(2): 225-237 (2010)
- [c30]Tim Kranich, Mladen Berekovic: NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems. DSD 2010: 53-59
- [c29]Dennis Bode, Mladen Berekovic, Axel Borkowski, Ludger Buker: QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration. DSD 2010: 141-146
- [c28]Jamin Naghmouchi, Daniele Paolo Scarpazza, Mladen Berekovic: Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization. ICS 2010: 337-348
2000 – 2009
- 2009
- [j17]Mladen Berekovic, Vipin Chaudhary, Alex Dean, Jason Fritts: Editorial. Microprocessors and Microsystems - Embedded Hardware Design 33(4): 233-234 (2009)
- [j16]Mladen Berekovic, Andreas Kanstein, Bingfeng Mei, Bjorn De Sutter: Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor. Microprocessors and Microsystems - Embedded Hardware Design 33(4): 290-294 (2009)
- [j15]Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jos Hulzink, Jef L. van Meerbergen: Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring. Signal Processing Systems 57(1): 107-119 (2009)
- [c27]Andreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic: Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing. ASAP 2009: 177-182
- [c26]Christian Bachmann, Andreas Genser, Jos Hulzink, Mladen Berekovic, Christian Steger: A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing. DATE 2009: 1614-1619
- [e3]Mladen Berekovic, Christian Müller-Schloer, Christian Hochberger, Stephan Wong (Eds.): Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings. Lecture Notes in Computer Science 5455, Springer 2009, ISBN 978-3-642-00453-7
- 2008
- [j14]Mladen Berekovic, Christian Hochberger, Andreas Koch: Rekonfigurierbare Architekturen. Informatik Spektrum 31(4): 344-347 (2008)
- [j13]Mladen Berekovic, Andy D. Pimentel, Timo D. Hämäläinen: Editorial. Journal of Systems Architecture - Embedded Systems Design 54(11): 1017-1018 (2008)
- [j12]Mladen Berekovic, Tim Niggemeier: A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance. Signal Processing Systems 50(2): 201-229 (2008)
- [c25]Andres Garcia, Mladen Berekovic, Tom Vander Aa: Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor. ASAP 2008: 245-250
- [c24]Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras: Low power microarchitecture with instruction reuse. Conf. Computing Frontiers 2008: 149-158
- [c23]Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev: Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array. HiPEAC 2008: 66-81
- [c22]Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael De Nil, Jef L. van Meerbergen: Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP. HiPEAC 2008: 82-96
- [c21]Mladen Berekovic, Frank Bouwens, Tom Vander Aa, Diederik Verkest: Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor. PATMOS 2008: 449-457
- [e2]Mladen Berekovic, Nikitas J. Dimopoulos, Stephan Wong (Eds.): Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings. Lecture Notes in Computer Science 5114, Springer 2008, ISBN 978-3-540-70549-9
- 2007
- [c20]Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev: Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. ARC 2007: 1-13
- [c19]Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic: MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture. ARC 2007: 26-38
- [c18]Lennart Yseboodt, Michael De Nil, Mladen Berekovic: Electrocardiogram on Wireless Sensor Nodes. Power-aware Computing Systems 2007
- [c17]C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet: Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. DATE 2007: 177-182
- [c16]Mladen Berekovic: Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring. DSD 2007: 16-18
- [c15]Matthias Hartmann, Vasileios (Vassilis) Pantazis, Tom Vander Aa, Mladen Berekovic, Christian Hochberger, Bjorn De Sutter: Still Image Processing on Coarse-Grained Reconfigurable Array Architectures. ESTImedia 2007: 67-72
- [c14]Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jef L. van Meerbergen: Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring. SAMOS 2007: 385-395
- [e1]Stamatis Vassiliadis, Mladen Berekovic, Timo D. Hämäläinen (Eds.): Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings. Lecture Notes in Computer Science 4599, Springer 2007, ISBN 978-3-540-73622-6
- 2006
- [c13]Bjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim, Sukjin Kim: Hardware and a Tool Chain for ADRES. ARC 2006: 425-430
- [c12]Mladen Berekovic, Tim Niggemeier: A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme. SAMOS 2006: 289-298
- 2005
- [b1]Mladen Berekovic: Eine skalierbare, verteilte Prozessor-Architektur mit simultanem multi-threading für Anwendungen der digitalen Signalverarbeitung. University of Hanover 2005, ISBN 3-18-337709-8, pp. 1-195
- [j11]Hans-Joachim Stolberg, Mladen Berekovic, Sören Moch, Lars Friebe, Mark Bernd Kulaczewski, Sebastian Flügel, Heiko Klußmann, Andreas Dehnhardt, Peter Pirsch: HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing. VLSI Signal Processing 41(1): 9-20 (2005)
- [j10]Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch: A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications. VLSI Signal Processing 41(2): 139-151 (2005)
- 2004
- [j9]Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, Andreas Dehnhardt, Peter Pirsch: HIBRID-SOC: a multi-core architecture for image and video applications. SIGARCH Computer Architecture News 32(3): 55-61 (2004)
- [j8]Mladen Berekovic, Sören Moch, Peter Pirsch: A scalable, clustered SMT processor for digital signal processing. SIGARCH Computer Architecture News 32(3): 62-69 (2004)
- 2003
- [c11]Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch: HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. DATE 2003: 20008-20013
- [c10]Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Mark Bernd Kulaczewski, Peter Pirsch: HiBRID-SoC: a multi-core architecture for image and video applications. ICIP (3) 2003: 101-104
- [c9]Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch: HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. VLSI-SOC 2003: 155-160
- 2002
- [j7]Mladen Berekovic, Hans-Joachim Stolberg, Peter Pirsch: Multicore system-on-chip architecture for MPEG-4 streaming video. IEEE Trans. Circuits Syst. Video Techn. 12(8): 688-699 (2002)
- [j6]Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo: Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing. VLSI Signal Processing 31(2): 157-171 (2002)
- [c8]Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch: A platform-independent methodology for performance estimation of streaming media applications. ICME (2) 2002: 105-108
- 2001
- [c7]Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch, Holger Runge: Implementing The MPEG-4 Advanced Simple Profile For Streaming Video Applications. ICME 2001
- 2000
- [c6]Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo: Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. ASAP 2000: 15-24
- [c5]Christoph Heer, Carolina Miro, Anne Lafage, Mladen Berekovic, Giovanni Ghigo, Thorsten Selinger, Kai-Immo Wels: Coprocessor architecture for MPEG-4 video object rendering. VCIP 2000: 1451-1458
1990 – 1999
- 1999
- [j5]Mladen Berekovic, Helge Kloos, Peter Pirsch: Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications. VLSI Signal Processing 22(1): 31-43 (1999)
- [j4]S. Bauer, Johannes Kneip, T. Mlasko, Bernd Schmale, J. Vollmer, A. Hutter, Mladen Berekovic: The MPEG-4 Multimedia Coding Standard: Algorithms, Architectures and Applications. VLSI Signal Processing 23(1): 7-26 (1999)
- [j3]Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack: Instruction Set Extensions for MPEG-4 Video. VLSI Signal Processing 23(1): 27-49 (1999)
- [c4]Helge Kloos, Mladen Berekovic, Peter Pirsch: Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen. ARCS 1999: 5-14
- [c3]Mladen Berekovic, K. Jacob, Peter Pirsch: Architecture of a hardware module for MPEG-4 shape decoding. ISCAS (1) 1999: 157-160
- 1998
- [j2]Mladen Berekovic, Peter Pirsch, Johannes Kneip: An Algorithm-Hardware-System Approach to VLIW Multimedia Processors. VLSI Signal Processing 20(1-2): 163-180 (1998)
- [c2]Mladen Berekovic, Peter Pirsch: An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing. Computer Graphics International 1998: 411-
- [c1]Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch: Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. DAC 1998: 56-61
- 1997
- [j1]Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch: An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor. VLSI Signal Processing 16(1): 31-40 (1997)
Coauthor Index
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last updated on 2013-05-17 21:54 CEST by the dblp team