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 | 1991 | |
|---|---|---|
| j5 |      | C. Leonard Berman, Louise Trevillyan: Global flow optimization in automatic logic design. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 557-564 (1991) |
| j4 | | C. Leonard Berman: Circuit width, register allocation, and ordered binary decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1059-1066 (1991) |
| 1989 | ||
| j3 | | Ravi Nair, C. Leonard Berman, Peter S. Hauge, Ellen J. Yoffa: Generation of performance constraints for layout. IEEE Trans. on CAD of Integrated Circuits and Systems 8(8): 860-874 (1989) |
| 1986 | ||
| j2 | | Louise Trevillyan, William H. Joyner Jr., C. Leonard Berman: Global Flow Analysis in Automatic Logic Design. IEEE Trans. Computers 35(1): 77-81 (1986) |
| 1981 | ||
| j1 | | John A. Darringer, William H. Joyner Jr., C. Leonard Berman, Louise Trevillyan: Logic Synthesis Through Local Transformations. IBM Journal of Research and Development 25(4): 272-280 (1981) |
| 1 | John A. Darringer | |
| 2 | Peter S. Hauge | |
| 3 | William H. Joyner Jr. | |
| 4 | Ravi Nair | |
| 5 | Louise Trevillyan | |
| 6 | Ellen J. Yoffa |
Colors in the list of coauthors
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