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Sarvesh Bhardwaj
2010 – today
- 2010
[j9]Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Frank Liu, Yu Cao: The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. IEEE Trans. VLSI Syst. 18(2): 173-183 (2010)- [j8]Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. IEEE Trans. VLSI Syst. 18(6): 988-997 (2010)
2000 – 2009
- 2009
- [j7]Satyajayant Misra, Guoliang Xue, Sarvesh Bhardwaj: Secure and Robust Localization in a Wireless Ad Hoc Environment. IEEE T. Vehicular Technology 58(3): 1480-1489 (2009)
- 2008
- [j6]Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula: Scalable model for predicting the effect of negative bias temperature instability for reliable design. IET Circuits, Devices & Systems 2(4): 361-371 (2008)
- [j5]Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory. J. Low Power Electronics 4(1): 68-80 (2008)
- [j4]Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 445-455 (2008)
- [j3]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel: A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1812-1825 (2008)
- [c17]Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design 2008: 515-520
- [c16]Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Power Reduction of Functional Units Considering Temperature and Process Variations. VLSI Design 2008: 533-539
- 2007
- [c15]Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao: The Impact of NBTI on the Performance of Combinational and Sequential Circuits. DAC 2007: 364-369
- [c14]Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula: Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. PATMOS 2007: 125-137
- [c13]Sarma B. K. Vrudhula, Sarvesh Bhardwaj: Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. VLSI Design 2007: 9
- [c12]Sarvesh Bhardwaj, Sarma B. K. Vrudhula: A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. VLSI Design 2007: 589-594
- 2006
- [j2]Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula: Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. J. Low Power Electronics 2(2): 240-250 (2006)
- [c11]Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula: Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. ASP-DAC 2006: 953-958
- [c10]Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda: Stochastic variational analysis of large power grids considering intra-die correlations. DAC 2006: 211-216
- [c9]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao: Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. DAC 2006: 791-796
- [c8]Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula: A framework for statistical timing analysis using non-linear delay and slew models. ICCAD 2006: 225-230
- [c7]Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula: LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. ISQED 2006: 717-722
- 2005
- [j1]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1784-1794 (2005)
- [c6]Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang: An efficient combinationality check technique for the synthesis of cyclic combinational circuits. ASP-DAC 2005: 212-215
- [c5]Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Leakage minimization of nano-scale circuits in the presence of systematic and random variations. DAC 2005: 541-546
- [c4]Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. ICCAD 2005: 713-718
- 2004
- [c3]Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj: Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. VLSI Design 2004: 240-
- 2003
- [c2]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: AU: Timing Analysis Under Uncertainty. ICCAD 2003: 615-620
- 2002
- [c1]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Estimation of signal arrival times in the presence of delay noise. ICCAD 2002: 418-422
Coauthor Index
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last updated on 2013-05-09 22:04 CEST by the dblp team