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Jayaram Bhasker
2000 – 2009
- 2004
[c4]Stephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden: Improving Design and Verification Productivity with VHDL-200x. DATE 2004: 332-335
1990 – 1999
- 1996
- [b1]Jayaram Bhasker: Die VHDL-Syntax. Markt und Technik 1996, ISBN 978-3-8272-9528-6
- 1995
- [j9]Muhammad K. Dhodhi, Frank H. Hielscher, Robert H. Storer, Jayaram Bhasker: Datapath synthesis using a problem-space genetic algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 934-944 (1995)
- 1994
- [j8]Jayaram Bhasker, Tariq Samad, Douglas B. West: Size, chromatic number, and connectivity. Graphs and Combinatorics 10(2-4): 209-213 (1994)
- 1991
- [j7]Rolf Ernst, Jayaram Bhasker: Simulation-Based Verification for High-Level Synthesis. IEEE Design & Test of Computers 8(1): 14-20 (1991)
- 1990
- [j6]Jayaram Bhasker, Huan-Chih Lee: An Optimizer for Hardware Synthesis. IEEE Design & Test of Computers 7(5): 20-36 (1990)
1980 – 1989
- 1989
- [j5]Jayaram Bhasker, Sartaj Sahni: Via Assignment in Single-Row Routing. IEEE Trans. Computers 38(1): 142-149 (1989)
- 1988
- [j4]Jayaram Bhasker, Sartaj Sahni: A Linear Algorithm to Find a Rectangular Dual of a Planar Triangulated Graph. Algorithmica 3: 247-278 (1988)
- [j3]Jayaram Bhasker: Implementation of an optimizing compiler for VHDL. SIGPLAN Notices 23(1): 92-108 (1988)
- [j2]Jayaram Bhasker: Process-graph Analyser: A Front-end Tool for VHDL Behavioural Synthesis. Softw., Pract. Exper. 18(5): 469-483 (1988)
- 1987
- [j1]Jayaram Bhasker, Sartaj Sahni: A linear time algorithm to check for the existence of a rectangular dual of a planar triangulated graph. Networks 17(3): 307-317 (1987)
- [c3]Jayaram Bhasker: An algorithm for microcode compaction of VHDL behavioral descriptions. MICRO 1987: 54-58
- [c2]
- 1986
- [c1]Jayaram Bhasker, Sartaj Sahni: A linear algorithm to find a rectangular dual of a planar triangulated graph. DAC 1986: 108-114
Coauthor Index
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last updated on 2013-01-24 21:47 CET by the dblp team