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 | 2011 | |
|---|---|---|
| c1 |      | Reid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski: A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers. ISSCC 2011: 84-86 |
| 2005 | ||
| j3 | | Cameron McNairy, Rohit Bhatia: Montecito: A Dual-Core, Dual-Thread Itanium Processor. IEEE Micro 25(2): 10-20 (2005) |
| 2004 | ||
| j2 | | Carl Scafidi, J. Douglas Gibson, Rohit Bhatia: Validating the Itanium 2 Exception Control Unit: A Unit-Level Approach. IEEE Design & Test of Computers 21(2): 94-101 (2004) |
| 2000 | ||
| j1 | | Christopher Sadler, Sandeep K. S. Gupta, Rohit Bhatia: Applying predication to efficiently handle runtime class testing. SIGARCH Computer Architecture News 28(1): 34-42 (2000) |
| 1 | Larry Biro | |
| 2 | William J. Bowhill | |
| 3 | Eric S. Fetzer | |
| 4 | J. Douglas Gibson | |
| 5 | Paul E. Gronowski | |
| 6 | Tom Grutkowski | |
| 7 | Sandeep K. S. Gupta | |
| 8 | Cameron McNairy | |
| 9 | Reid J. Riedlinger | |
| 10 | Christopher Sadler | |
| 11 | Carl Scafidi |
Colors in the list of coauthors
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