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Prasenjit Biswas
2010 – today
- 2010
[c10]Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. ISVLSI 2010: 161-166- [c9]Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. ICSAMOS 2010: 265-272
2000 – 2009
- 2009
- [j6]Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan: REDEFINE: Runtime reconfigurable polymorphic ASIC. ACM Trans. Embedded Comput. Syst. 9(2) (2009)
- [c8]Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan: Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. CASES 2009: 127-136
- [c7]Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan: Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. SoCC 2009: 251-254
- 2000
- [j5]Prasenjit Biswas, Atsushi Hasegawa, Srinivas Mandaville, Mark Debbage, Andy Sturges, Fumio Arakawa, Yasuhiko Saito, Kunio Uchiyama: SH-5: The 64-Bit SuperH Architecture. IEEE Micro 20(4): 28-39 (2000)
1990 – 1999
- 1994
- [j4]Surapong Auwatanamongkol, Andrzej Ciepielewski, Prasenjit Biswas: Cut and Side-Effects in a Data-Driven Implementation of Prolog. New Generation Comput. 12(3): 223-250 (1994)
- 1993
- [j3]Dagung Lu, Prasenjit Biswas: An extended scheduling technique for software pipelining. Microprocessing and Microprogramming 37(1-5): 99-103 (1993)
- [c6]Behrooz Shirazi, Krishna M. Kavi, Ali R. Hurson, Prasenjit Biswas: PARSA: A Parallel Program Scheduling and Assessment Environment. ICPP 1993: 68-72
- 1991
- [c5]Surapong Auwatanamongkol, Prasenjit Biswas: A Hybrid Architecture and Adaptive Scheduling for Parallel Execution of Logic Programs. ICPP (1) 1991: 17-20
1980 – 1989
- 1988
- [c4]Prasenjit Biswas, Chien-Chao Tseng: LogDf: A Data-Driven Abstract Machine Model for Parallel Execution of Logic Programs. FGCS 1988: 1059-1070
- [c3]Prasenjit Biswas, Shyh-Chang Su, David Y. Y. Yun: A Scalable Abstract Machine Model to Support Limited-OR (LOR) / Restricted-AND Parallelism (RAP) in Logic Programs. ICLP/SLP 1988: 1160-1179
- [c2]Chien-Chao Tseng, Prasenjit Biswas: A Data-Driven Parallel Execution Model for Logic Programs. ICLP/SLP 1988: 1204-1222
- [c1]Prasenjit Biswas, Arun K. Majumdar: A Fuzzy Hybrid Model for Pattern Classification. Pattern Recognition 1988: 183-192
- 1985
- [j2]Prasenjit Biswas, Subrata Dasgupta: Architectural support for variable addressing in Ada - A design approach. International Journal of Parallel Programming 14(1): 51-72 (1985)
- 1983
- [j1]Prasenjit Biswas, Arun K. Majumdar: A supervised learning algorithm for hierarchical classification of fuzzy patterns. Inf. Sci. 31(2): 91-106 (1983)
Coauthor Index
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last updated on 2012-12-02 20:40 CET by the dblp team