Per Bjesse

Per Bjesse, Anna Slobodová (Eds.): International Conference on Formal Methods in Computer-Aided Design, FMCAD '11, Austin, TX, USA, October 30 - November 02, 2011. FMCAD Inc. 2011, isbn 978-0-9835678-1-3

Per Bjesse: Word level bitwidth reduction for unbounded hardware model checking. Formal Methods in System Design 35(1): 56-72 (2009)

Per Bjesse: A Practical Approach to Word Level Model Checking of Industrial Netlists. CAV 2008: 446-458

Per Bjesse: Word-Level Sequential Memory Abstraction for Model Checking. FMCAD 2008: 1-9

In-Ho Moon, Per Bjesse, Carl Pixley: A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. DATE 2007: 1170-1175

In-Ho Moon, Per Bjesse, Carl Pixley: Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces. HLDVT 2006: 170-175

Per Bjesse, James H. Kukula: Automatic generalized phase abstraction for formal verification. ICCAD 2005: 1076-1082

Per Bjesse, James H. Kukula: Using Counter Example Guided Abstraction Refinement to Find Complex Bugs. DATE 2004: 156-161

Per Bjesse, Arne Borälv: DAG-aware circuit compression for formal verification. ICCAD 2004: 42-49

Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna: Design automation with mixtures of proof strategies for propositional logic. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1042-1048 (2003)

Per Bjesse, James H. Kukula, Robert F. Damiano, Ted Stanion, Yunshan Zhu: Guiding SAT Diagnosis with Tree Decompositions. SAT 2003: 315-329

Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna: A proof engine approach to solving combinational design automation problems. DAC 2002: 725-730

Per Bjesse: Industrial Model Checking Based on Satisfiability Solvers. SPIN 2002: 240

Per Bjesse, Tim Leonard, Abdel Mokkedem: Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers. CAV 2001: 454-464

Per Bjesse, Koen Claessen: SAT-Based Verification without State Space Traversal. FMCAD 2000: 372-389

Parosh Aziz Abdulla, Per Bjesse, Niklas Eén: Symbolic Reachability Analysis Based on SAT-Solvers. TACAS 2000: 411-425

Per Bjesse: Automatic Verification of Combinatorial and Pipelined FFT. CAV 1999: 380-393

Per Bjesse, Koen Claessen, Mary Sheeran, Satnam Singh: Lava: Hardware Design in Haskell. ICFP 1998: 174-184