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David Blaauw
David T. Blaauw
2010 – today
- 2013
[j80]Matthew Fojtik, David Fick, Yejoong Kim, Nathaniel Ross Pinckney, David Money Harris, David Blaauw, Dennis Sylvester: Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction. J. Solid-State Circuits 48(1): 66-81 (2013)- [j79]David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, David Blaauw, Dennis Sylvester: Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS. J. Solid-State Circuits 48(1): 104-117 (2013)
- [j78]Yoonmyung Lee, Suyoung Bang, Inhee Lee, Yejoong Kim, Gyouho Kim, Mohammad Hassan Ghaed, Pat Pannuto, Prabal Dutta, Dennis Sylvester, David Blaauw: A Modular 1 mm3 Die-Stacked Sensing Platform With Low Power I2C Inter-Die Communication and Multi-Modal Energy Harvesting. J. Solid-State Circuits 48(1): 229-243 (2013)
- [j77]Matthew Fojtik, Daeyeon Kim, Gregory K. Chen, Yu-Shiang Lin, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, David Blaauw, Dennis Sylvester: A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells. J. Solid-State Circuits 48(3): 801-813 (2013)
- [j76]Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Dennis Sylvester, David Blaauw, Trevor N. Mudge: Centip3De: A 64-Core, 3D Stacked Near-Threshold System. IEEE Micro 33(2): 8-16 (2013)
- [j75]Cheng Zhuo, Dennis Sylvester, David Blaauw: A Statistical Framework for Post-Fabrication Oxide Breakdown Reliability Prediction and Management. IEEE Trans. on CAD of Integrated Circuits and Systems 32(4): 630-643 (2013)
- [c219]Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge: Scaling towards kilo-core processors with asymmetric high-radix topologies. HPCA 2013: 496-507
- [c218]Dongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, David Blaauw, Dennis Sylvester: A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS. ISSCC 2013: 166-167
- [c217]Dong-Woo Jee, Dennis Sylvester, David Blaauw, Jae-Yoon Sim: A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms. ISSCC 2013: 188-189
- [c216]Seon-Kyoo Lee, Seung-Hun Lee, Dennis Sylvester, David Blaauw, Jae-Yoon Sim: A 95fJ/b current-mode transceiver for 10mm on-chip interconnect. ISSCC 2013: 262-263
- [c215]Suyoung Bang, Allan Wang, Bharan Giridhar, David Blaauw, Dennis Sylvester: A fully integrated successive-approximation switched-capacitor DC-DC converter with 31mV output voltage resolution. ISSCC 2013: 370-371
- [c214]Gyouho Kim, Mahmood Barangi, Zhiyoong Foo, Nathaniel Ross Pinckney, Suyoung Bang, David Blaauw, Dennis Sylvester: A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregation. ISSCC 2013: 480-481
- 2012
- [j74]Korey Sewell, Ronald G. Dreslinski, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David Blaauw, Trevor N. Mudge: Swizzle-Switch Networks for Many-Core Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 278-294 (2012)
- [j73]Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester: A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS. J. Solid-State Circuits 47(1): 23-34 (2012)
- [j72]Mingoo Seok, Gyouho Kim, David Blaauw, Dennis Sylvester: A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V. J. Solid-State Circuits 47(10): 2534-2545 (2012)
- [j71]Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David Blaauw, Jin Hu, Gregory K. Chen: A Reliable Routing Architecture and Algorithm for NoCs. IEEE Trans. on CAD of Integrated Circuits and Systems 31(5): 726-739 (2012)
- [j70]Dongsuk Jeon, Mingoo Seok, Zhengya Zhang, David Blaauw, Dennis Sylvester: Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems. IEEE Trans. on Circuits and Systems 59-II(12): 952-956 (2012)
- [j69]Mingoo Seok, Scott Hanson, David Blaauw, Dennis Sylvester: Sleep Mode Analysis and Optimization With Minimal-Sized Power Gating Switch for Ultra-Low ${V}_{\rm dd}$ Operation. IEEE Trans. VLSI Syst. 20(4): 605-615 (2012)
- [j68]Prashant Singh, Eric Karl, David Blaauw, Dennis Sylvester: Compact Degradation Sensors for Monitoring NBTI and Oxide Degradation. IEEE Trans. VLSI Syst. 20(9): 1645-1655 (2012)
- [c213]Ronald G. Dreslinski, Thomas Manville, Korey Sewell, Reetuparna Das, Nathaniel Ross Pinckney, Sudhir Satpathy, David Blaauw, Dennis Sylvester, Trevor N. Mudge: XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems. PACT 2012: 75-86
- [c212]Suyoung Bang, David Blaauw, Dennis Sylvester, Massimo Alioto: Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems. CICC 2012: 1-4
- [c211]Zhiyoong Foo, David Devescery, Mohammad Hassan Ghaed, Inhee Lee, Abishek Madhavan, Youn Sung Park, Aswin Rao, Zach Renner, Nathan Roberts, Aaron Schulman, Vikas Vinay, Michael Wieckowski, Dongmin Yoon, Cliff Schmidt, Thomas Schmid, Prabal Dutta, Peter Chen, David Blaauw: A low-cost audio computer for information dissemination among illiterate people groups. CICC 2012: 1-4
- [c210]Gyouho Kim, Yoonmyung Lee, Suyoung Bang, Inhee Lee, Yejoong Kim, Dennis Sylvester, David Blaauw: A 695 pW standby power optical wake-up receiver for wireless sensor nodes. CICC 2012: 1-4
- [c209]Sudhir Satpathy, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David Blaauw: High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service. DAC 2012: 406-411
- [c208]Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Yongjun Park, Chaitali Chakrabarti, Scott A. Mahlke, David Blaauw, Trevor N. Mudge: Process variation in near-threshold wide SIMD architectures. DAC 2012: 980-987
- [c207]Yoonmyung Lee, Yejoong Kim, Dongmin Yoon, David Blaauw, Dennis Sylvester: Circuit and system design guidelines for ultra-low power sensor nodes. DAC 2012: 1037-1042
- [c206]Nathaniel Ross Pinckney, Korey Sewell, Ronald G. Dreslinski, David Fick, Trevor N. Mudge, Dennis Sylvester, David Blaauw: Assessing the performance limits of parallelized near-threshold computing. DAC 2012: 1147-1152
- [c205]Yejoong Kim, Yoonmyung Lee, Dennis Sylvester, David Blaauw: SLC: Split-control Level Converter for dense and stable wide-range voltage conversion. ESSCIRC 2012: 478-481
- [c204]Pat Pannuto, Yoonmyung Lee, Benjamin P. Kempke, Dennis Sylvester, David Blaauw, Prabal Dutta: Ultra-constrained sensor platform interfacing. IPSN 2012: 147-148
- [c203]Daeyeon Kim, Vikas Chandra, Robert C. Aitken, David Blaauw, Dennis Sylvester: An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs. ISLPED 2012: 91-96
- [c202]David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David Blaauw: Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores. ISSCC 2012: 190-192
- [c201]Dongmin Yoon, Dennis Sylvester, David Blaauw: A 5.58nW 32.768kHz DLL-assisted XO for real-time clocks in wireless sensing applications. ISSCC 2012: 366-368
- [c200]Yoonmyung Lee, Gyouho Kim, Suyoung Bang, Yejoong Kim, Inhee Lee, Prabal Dutta, Dennis Sylvester, David Blaauw: A modular 1mm3 die-stacked sensing platform with optical communication and multi-modal energy harvesting. ISSCC 2012: 402-404
- [c199]Sudhir Satpathy, Korey Sewell, Thomas Manville, Yen-Po Chen, Ronald G. Dreslinski, Dennis Sylvester, Trevor N. Mudge, David Blaauw: A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS. ISSCC 2012: 478-480
- [c198]Matthew Fojtik, David Fick, Yejoong Kim, Nathaniel Ross Pinckney, David Money Harris, David Blaauw, Dennis Sylvester: Bubble Razor: An architecture-independent approach to timing-error detection and correction. ISSCC 2012: 488-490
- [c197]Hassan Ghaed, Gregory K. Chen, David Blaauw, Dennis Sylvester: Analysis and measurement of the stability of dual-resonator oscillators. RWS 2012: 219-222
- 2011
- [j67]Mingoo Seok, Gregory K. Chen, Scott Hanson, Michael Wieckowski, David T. Blaauw, Dennis Sylvester: CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(1): 42-49 (2011)
- [j66]Mingoo Seok, David T. Blaauw, Dennis Sylvester: Robust Clock Network Design Methodology for Ultra-Low Voltage Operations. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 120-130 (2011)
- [j65]David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David Blaauw: A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation. J. Solid-State Circuits 46(1): 18-31 (2011)
- [j64]David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David Blaauw: Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation". J. Solid-State Circuits 46(3): 705 (2011)
- [j63]Jae-sun Seo, David Blaauw, Dennis Sylvester: Crosstalk-Aware PWM-Based On-Chip Links With Self-Calibration in 65 nm CMOS. J. Solid-State Circuits 46(9): 2041-2052 (2011)
- [j62]Vineeth Veetil, Kaviraj Chopra, David Blaauw, Dennis Sylvester: Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 30(6): 852-865 (2011)
- [j61]Cheng Zhuo, Kaviraj Chopra, Dennis Sylvester, David Blaauw: Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 30(9): 1321-1334 (2011)
- [j60]Prashant Singh, Eric Karl, Dennis Sylvester, David Blaauw: Dynamic NBTI Management Using a 45 nm Multi-Degradation Sensor. IEEE Trans. on Circuits and Systems 58-I(9): 2026-2037 (2011)
- [j59]Jae-sun Seo, Himanshu Kaul, Ram Krishnamurthy, Dennis Sylvester, David Blaauw: A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect. IEEE Trans. VLSI Syst. 19(2): 264-273 (2011)
- [c196]Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester: Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design. DAC 2011: 990-995
- [c195]Mark Woh, Sudhir Satpathy, Ronald G. Dreslinski, Danny Kershaw, Dennis Sylvester, David Blaauw, Trevor N. Mudge: Low power interconnects for SIMD computers. DATE 2011: 600-605
- [c194]Chia-Hsiang Chen, Yejoong Kim, Zhengya Zhang, David Blaauw, Dennis Sylvester, H. Naeimi, S. Sandhu: A confidence-driven model for error-resilient computing. DATE 2011: 1608-1613
- [c193]Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester: Energy-optimized high performance FFT processor. ICASSP 2011: 1701-1704
- [c192]Gregory K. Chen, Michael Wieckowski, Daeyeon Kim, David Blaauw, Dennis Sylvester: A dense 45nm half-differential SRAM with lower minimum operating voltage. ISCAS 2011: 57-60
- [c191]Daeyeon Kim, Gregory K. Chen, Matthew Fojtik, Mingoo Seok, David Blaauw, Dennis Sylvester: A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme. ISCAS 2011: 69-72
- [c190]Daeyeon Kim, Vikas Chandra, Robert C. Aitken, David Blaauw, Dennis Sylvester: Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs. ISLPED 2011: 145-150
- [c189]Michael Wieckowski, Gregory K. Chen, Daeyeon Kim, David Blaauw, Dennis Sylvester: A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers. ISQED 2011: 87-90
- [c188]Yoonmyung Lee, Bharan Giridhar, Zhiyoong Foo, Dennis Sylvester, David Blaauw: A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization. ISSCC 2011: 46-48
- [c187]Gregory K. Chen, Hassan Ghaed, Razi-Ul Haque, Michael Wieckowski, Yejoong Kim, Gyouho Kim, David Fick, Daeyeon Kim, Mingoo Seok, Kensall Wise, David Blaauw, Dennis Sylvester: A cubic-millimeter energy-autonomous wireless intraocular pressure monitor. ISSCC 2011: 310-312
- [c186]Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester: A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining. ISSCC 2011: 342-344
- 2010
- [j58]Carlos Tokunaga, David Blaauw: Securing Encryption Systems With a Switched Capacitor Current Equalizer. J. Solid-State Circuits 45(1): 23-31 (2010)
- [j57]Scott Hanson, Zhiyoong Foo, David Blaauw, Dennis Sylvester: A 0.5 V Sub-Microwatt CMOS Image Sensor With Pulse-Width Modulation Read-Out. J. Solid-State Circuits 45(4): 759-767 (2010)
- [j56]Ronald G. Dreslinski, Michael Wieckowski, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits. Proceedings of the IEEE 98(2): 253-266 (2010)
- [j55]Gregory K. Chen, Scott Hanson, David Blaauw, Dennis Sylvester: Circuit Design Advances for Wireless Sensing Applications. Proceedings of the IEEE 98(11): 1808-1827 (2010)
- [j54]Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester: Victim Alignment in Crosstalk-Aware Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 261-274 (2010)
- [j53]Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Mechanical Stress Aware Optimization for Leakage Power Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 722-736 (2010)
- [j52]Gregory K. Chen, Dennis Sylvester, David Blaauw, Trevor N. Mudge: Yield-Driven Near-Threshold SRAM Design. IEEE Trans. VLSI Syst. 18(11): 1590-1598 (2010)
- [c185]Cheng Zhuo, Yung-Hsu Chang, Dennis Sylvester, David Blaauw: Design time body bias selection for parametric yield improvement. ASP-DAC 2010: 681-688
- [c184]Vivek Joshi, Kanak Agarwal, Dennis Sylvester, David Blaauw: Analyzing electrical effects of RTA-driven local anneal temperature variation. ASP-DAC 2010: 739-744
- [c183]Vivek Joshi, Michael Wieckowski, Gregory K. Chen, David Blaauw, Dennis Sylvester: Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOS. CICC 2010: 1-4
- [c182]Yoonmyung Lee, Gregory K. Chen, Scott Hanson, Dennis Sylvester, David Blaauw: Ultra-low power circuit techniques for a new class of sub-mm3 sensor nodes. CICC 2010: 1-8
- [c181]Prashant Singh, Eric Karl, Dennis Sylvester, David Blaauw: Dynamic NBTI management using a 45nm multi-degradation sensor. CICC 2010: 1-4
- [c180]Vivek Joshi, Valeriy Sukharev, Andres Torres, Kanak Agarwal, Dennis Sylvester, David Blaauw: Closed-form modeling of layout-dependent mechanical stress. DAC 2010: 673-678
- [c179]Vineeth Veetil, Yung-Hsu Chang, Dennis Sylvester, David Blaauw: Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization. DAC 2010: 793-798
- [c178]Cheng Zhuo, Dennis Sylvester, David Blaauw: Process variation and temperature-aware reliability management. DATE 2010: 580-585
- [c177]Michael Wieckowski, Dennis Sylvester, David Blaauw, Vikas Chandra, Sachin Idgunji, Cezary Pietrzyk, Robert C. Aitken: A black box method for stability analysis of arbitrary SRAM cell structures. DATE 2010: 795-800
- [c176]Zhiyoong Foo, David Devescery, Thomas Schmid, Nathan Clark, R. Frank, Mohammad Hassan Ghaed, Ye-Sheng Kuo, Inhee Lee, Youn Sung Park, Zach Renner, Nathaniel Slottow, Vikas Vinay, Michael Wieckowski, Dongmin Yoon, Cliff Schmidt, David Blaauw, Peter Chen, Prabal Dutta: A case for custom silicon in enabling low-cost information technology for developing regions. ACM DEV 2010: 22
- [c175]Vivek Joshi, Kanak Agarwal, David Blaauw, Dennis Sylvester: Analysis and optimization of SRAM robustness for double patterning lithography. ICCAD 2010: 25-31
- [c174]Cheng Zhuo, Kanak Agarwal, David Blaauw, Dennis Sylvester: Active learning framework for post-silicon variation extraction and test cost reduction. ICCAD 2010: 508-515
- [c173]Vineeth Veetil, Dennis Sylvester, David Blaauw: A lower bound computation method for evaluation of statistical design techniques. ICCAD 2010: 562-569
- [c172]Mingoo Seok, Scott Hanson, Michael Wieckowski, Gregory K. Chen, Yu-Shiang Lin, David Blaauw, Dennis Sylvester: Circuit design advances to enable ubiquitous sensing environments. ISCAS 2010: 285-288
- [c171]Mingoo Seok, David Blaauw, Dennis Sylvester: Clock network design for ultra-low power applications. ISLPED 2010: 271-276
- [c170]Jae-sun Seo, Ron Ho, Jon K. Lexau, Michael Dayringer, Dennis Sylvester, David Blaauw: High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS. ISSCC 2010: 182-183
- [c169]David Fick, Nurrachman Liu, Zhiyoong Foo, Matthew Fojtik, Jae-sun Seo, Dennis Sylvester, David Blaauw: In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter. ISSCC 2010: 188-189
- [c168]Prashant Singh, Zhiyoong Foo, Michael Wieckowski, Scott Hanson, Matthew Fojtik, David Blaauw, Dennis Sylvester: Early detection of oxide breakdown through in situ degradation sensing. ISSCC 2010: 190-191
- [c167]David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David Blaauw: A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation. ISSCC 2010: 284-285
- [c166]Gregory K. Chen, Matthew Fojtik, Daeyeon Kim, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, Dennis Sylvester, David Blaauw: Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells. ISSCC 2010: 288-289
2000 – 2009
- 2009
- [j51]Prashant Singh, Cheng Zhuo, Eric Karl, David Blaauw, Dennis Sylvester: Sensor-Driven Reliability and Wearout Management. IEEE Design & Test of Computers 26(6): 40-49 (2009)
- [j50]Rajeev R. Rao, Vivek Joshi, David Blaauw, Dennis Sylvester: Circuit optimization techniques to mitigate the effects of soft errors in combinational logic. ACM Trans. Design Autom. Electr. Syst. 15(1) (2009)
- [j49]Bo Zhai, Sanjay Pant, Leyla Nazhandali, Scott Hanson, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Todd M. Austin, Dennis Sylvester, David Blaauw: Energy-Efficient Subthreshold Processor Design. IEEE Trans. VLSI Syst. 17(8): 1127-1137 (2009)
- [c165]Yu-Shiang Lin, Dennis Sylvester, David Blaauw: Near-field communication using phase-locking and pulse signaling for millimeter-scale systems. CICC 2009: 563-566
- [c164]Mingoo Seok, Gyouho Kim, Dennis Sylvester, David Blaauw: A 0.5V 2.2pW 2-transistor voltage reference. CICC 2009: 577-580
- [c163]Shidhartha Das, David Blaauw, David M. Bull, Krisztián Flautner, Rob Aitken: Addressing design margins through error-tolerant circuits. DAC 2009: 11-12
- [c162]Ravikishore Gandikota, Li Ding, Peivand Tehrani, David Blaauw: Worst-case aggressor-victim alignment with current-source driver models. DAC 2009: 13-18
- [c161]Vineeth Veetil, Dennis Sylvester, David Blaauw, Saumil Shah, Steffen Rochel: Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence. DAC 2009: 154-159
- [c160]David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester: Vicis: a reliable network for unreliable silicon. DAC 2009: 812-817
- [c159]David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David Blaauw: A highly resilient routing algorithm for fault-tolerant NoCs. DATE 2009: 21-26
- [c158]Cheng Zhuo, David Blaauw, Dennis Sylvester: Post-fabrication measurement-driven oxide breakdown reliability prediction and management. ICCAD 2009: 441-448
- [c157]Ravikishore Gandikota, David Blaauw, Dennis Sylvester: Interconnect performance corners considering crosstalk noise. ICCD 2009: 231-237
- [c156]
- [c155]Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David Blaauw: Low power circuit design based on heterojunction tunneling transistors (HETTs). ISLPED 2009: 219-224
- [c154]Carlos Tokunaga, David Blaauw: Secure AES engine with a local switched-capacitor current equalizer. ISSCC 2009: 64-65
- [c153]Yu-Shiang Lin, Dennis Sylvester, David T. Blaauw: A 150pW program-and-hold timer for ultra-low-power sensor platforms. ISSCC 2009: 326-327
- [c152]Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reconfigurable Multicore Server Processors for Low Power Operation. SAMOS 2009: 247-254
- 2008
- [j48]Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw: A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 272-285 (2008)
- [j47]Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw: Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 481-494 (2008)
- [j46]David Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer: Statistical Timing Analysis: From Basic Principles to State of the Art. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 589-607 (2008)
- [j45]Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Multi-Mechanism Reliability Modeling and Management in Dynamic Systems. IEEE Trans. VLSI Syst. 16(4): 476-487 (2008)
- [j44]Prashant Singh, Jae-sun Seo, David Blaauw, Dennis Sylvester: Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect. IEEE Trans. VLSI Syst. 16(6): 673-677 (2008)
- [c151]Vineeth Veetil, Dennis Sylvester, David Blaauw: Efficient Monte Carlo based incremental statistical timing analysis. DAC 2008: 676-681
- [c150]Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Leakage power reduction using stress-enhanced layouts. DAC 2008: 912-917
- [c149]Ravikishore Gandikota, David Blaauw, Dennis Sylvester: Modeling crosstalk in statistical static timing analysis. DAC 2008: 974-979
- [c148]Brian Cline, Kaviraj Chopra, David Blaauw, Andres Torres, Savithri Sundareswaran: Transistor-Specific Delay Modeling for SSTA. DATE 2008: 592-597
- [c147]Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw: On the decreasing significance of large standard cells in technology mapping. ICCAD 2008: 116-121
- [c146]Brian Cline, Vivek Joshi, Dennis Sylvester, David Blaauw: STEEL: a technique for stress-enhanced standard cell library design. ICCAD 2008: 691-697
- [c145]Kaviraj Chopra, Cheng Zhuo, David Blaauw, Dennis Sylvester: A statistical approach for full-chip gate-oxide reliability analysis. ICCAD 2008: 698-705
- [c144]Yu-Shiang Lin, Scott Hanson, Fabio Albano, Carlos Tokunaga, Razi-Ul Haque, Kensall Wise, Ann Marie Sastry, David Blaauw, Dennis Sylvester: Low-voltage circuit design for widespread sensing applications. ISCAS 2008: 2558-2561
- [c143]Mingoo Seok, Dennis Sylvester, David Blaauw: Optimal technology selection for minimizing energy and variability in low voltage applications. ISLPED 2008: 9-14
- [c142]Cheng Zhuo, David Blaauw, Dennis Sylvester: Variation-aware gate sizing and clustering for post-silicon optimized circuits. ISLPED 2008: 105-110
- [c141]Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Stress aware layout optimization. ISPD 2008: 168-174
- [c140]Vineeth Veetil, Dennis Sylvester, David Blaauw: Fast and Accurate Waveform Analysis with Current Source Models. ISQED 2008: 53-56
- [c139]Eric Karl, Dennis Sylvester, David Blaauw: Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures. ISQED 2008: 391-395
- [c138]Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David Blaauw, Dennis Sylvester, Krisztián Flautner: Reconfigurable energy efficient near threshold cache architectures. MICRO 2008: 459-470
- 2007
- [j43]Sanjay Pant, Eli Chiprout, David Blaauw: Power Grid Physics and Implications for CAD. IEEE Design & Test of Computers 24(3): 246-254 (2007)
- [j42]Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester: Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 468-479 (2007)
- [c137]Ronald G. Dreslinski, Bo Zhai, Trevor N. Mudge, David Blaauw, Dennis Sylvester: An Energy Efficient Parallel Architecture Using Near Threshold Operation. PACT 2007: 175-188
- [c136]Sanjay Pant, David Blaauw: Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks. ASP-DAC 2007: 757-762
- [c135]Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer: Top-k Aggressors Sets in Delay Noise Analysis. DAC 2007: 174-179
- [c134]Mingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw: Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design. DAC 2007: 694-699
- [c133]Scott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw: Nanometer Device Scaling in Subthreshold Circuits. DAC 2007: 700-705
- [c132]Gregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim: Yield-driven near-threshold SRAM design. ICCAD 2007: 660-666
- [c131]Vivek Joshi, David Blaauw, Dennis Sylvester: Soft-edge flip-flops for improved timing yield: design and optimization. ICCAD 2007: 667-673
- [c130]Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada: Victim alignment in crosstalk aware timing analysis. ICCAD 2007: 698-704
- [c129]Bo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge, Dennis Sylvester: Energy efficient near-threshold chip multi-processing. ISLPED 2007: 32-37
- [c128]Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy: A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED 2007: 68-73
- [c127]Jae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw: Self-Time Regenerators for High-Speed and Low-Power Interconnect. ISQED 2007: 621-626
- [c126]
- [c125]
- [i2]Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction. CoRR abs/0710.4679 (2007)
- [i1]Aseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing. CoRR abs/0710.4697 (2007)
- 2006
- [j41]Dennis Sylvester, David Blaauw, Eric Karl: ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon. IEEE Design & Test of Computers 23(6): 484-490 (2006)
- [j40]Scott Hanson, Bo Zhai, Kerry Bernstein, David Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester: Ultralow-voltage, minimum-energy CMOS. IBM Journal of Research and Development 50(4-5): 469-490 (2006)
- [j39]Kanak Agarwal, Dennis Sylvester, David Blaauw: Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 892-901 (2006)
- [j38]Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw: Statistical interconnect metrics for physical-design optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1273-1288 (2006)
- [j37]Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Analytical yield prediction considering leakage/performance correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1685-1695 (2006)
- [j36]Dongwoo Lee, David Blaauw, Dennis Sylvester: Runtime Leakage Minimization Through Probability-Aware Optimization. IEEE Trans. VLSI Syst. 14(10): 1075-1088 (2006)
- [c124]Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reliability modeling and management in dynamic microprocessor-based systems. DAC 2006: 1057-1060
- [c123]Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester: An efficient static algorithm for computing the soft error rates of combinational circuits. DATE 2006: 164-169
- [c122]Sarvesh H. Kulkarni, Dennis Sylvester, David Blaauw: A statistical framework for post-silicon tuning through body bias clustering. ICCAD 2006: 39-46
- [c121]Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao: Analysis and modeling of CD variation for statistical static timing. ICCAD 2006: 60-66
- [c120]Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester: A new statistical max operation for propagating skewness in statistical timing analysis. ICCAD 2006: 237-243
- [c119]Rajeev R. Rao, David Blaauw, Dennis Sylvester: Soft error reduction in combinational logic using gate resizing and flipflop selection. ICCAD 2006: 502-509
- [c118]Sanjay Pant, David Blaauw: An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks. ICCD 2006
- [c117]David Blaauw, Bo Zhai: Energy efficient design for subthreshold supply voltage operation. ISCAS 2006
- [c116]Scott Hanson, Dennis Sylvester, David Blaauw: A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. ISLPED 2006: 338-341
- [c115]Scott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang: Energy optimality and variability in subthreshold design. ISLPED 2006: 363-365
- [c114]Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester: Logic SER Reduction through Flipflop Redesign. ISQED 2006: 611-616
- [c113]Mini Nanua, David Blaauw: Receiver Modeling for Static Functional Crosstalk Analysis. PATMOS 2006: 329-339
- 2005
- [j35]Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan: Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Design & Test of Computers 22(4): 376-385 (2005)
- [j34]Dongwoo Lee, David Blaauw, Dennis Sylvester: Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1014-1029 (2005)
- [j33]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1784-1794 (2005)
- [j32]Nam Sung Kim, David Blaauw, Trevor N. Mudge: Quantitative analysis and optimization techniques for on-chip cache leakage power. IEEE Trans. VLSI Syst. 13(10): 1147-1156 (2005)
- [j31]Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner: The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. IEEE Trans. VLSI Syst. 13(11): 1239-1252 (2005)
- [j30]Rajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester: Bus encoding for total power reduction using a leakage-aware buffer configuration. IEEE Trans. VLSI Syst. 13(12): 1376-1383 (2005)
- [c112]Todd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge: Opportunities and challenges for better than worst-case design. ASP-DAC 2005: 2-7
- [c111]Kanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan: Achieving continuous VT performance in a dual VT process. ASP-DAC 2005: 393-398
- [c110]Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw: Statistical modeling of cross-coupling effects in VLSI interconnects. ASP-DAC 2005: 503-506
- [c109]David Blaauw, Anirudh Devgan, Farid N. Najm: Leakage power: trends, analysis and avoidance. ASP-DAC 2005
- [c108]Dongwoo Lee, David Blaauw, Dennis Sylvester: Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. ASP-DAC 2005: 399-404
- [c107]Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David Blaauw: A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. CASES 2005: 249-256
- [c106]Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov: Circuit optimization using statistical static timing analysis. DAC 2005: 321-324
- [c105]Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540
- [c104]
- [c103]Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction. DATE 2005: 80-85
- [c102]Aseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing. DATE 2005: 400-405
- [c101]Amit Jain, David Blaauw: Slack borrowing in flip-flop based sequential circuits. ACM Great Lakes Symposium on VLSI 2005: 96-101
- [c100]Sanjay Pant, David Blaauw: Static timing analysis considering power supply variations. ICCAD 2005: 365-371
- [c99]Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov: Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. ICCAD 2005: 705-712
- [c98]Amit Jain, David Blaauw, Vladimir Zolotov: Accurate delay computation for noisy waveform shapes. ICCAD 2005: 947-953
- [c97]Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester: Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. ICCAD 2005: 1023-1028
- [c96]Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw: Energy Optimization of Subthreshold-Voltage Sensor Network Processors. ISCA 2005: 197-207
- [c95]Eric Karl, Dennis Sylvester, David Blaauw: Timing error correction techniques for voltage-scalable on-chip memories. ISCAS (4) 2005: 3563-3566
- [c94]Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester: Analysis and mitigation of variability in subthreshold design. ISLPED 2005: 20-25
- [c93]Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif: An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93
- [c92]David Roberts, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Error Analysis for the Support of Robust Voltage Scaling. ISQED 2005: 65-70
- [c91]Mini Nanua, David Blaauw, Chanhee Oh: Leakage Current Modeling in PD SOI Circuits. ISQED 2005: 113-117
- [c90]Harmander Deogun, Dennis Sylvester, David Blaauw: Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate. ISQED 2005: 175-180
- 2004
- [j29]Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Making Typical Silicon Matter with Razor. IEEE Computer 37(3): 57-65 (2004)
- [j28]Todd M. Austin, David Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne Wolf: Mobile Supercomputers. IEEE Computer 37(5): 81-83 (2004)
- [j27]Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner: Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24(6): 10-20 (2004)
- [j26]Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driver output model for on-chip RLC transmission lines. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 128-136 (2004)
- [j25]Aseem Agarwal, Vladimir Zolotov, David Blaauw: Statistical clock skew analysis considering intradie-process variations. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1231-1242 (2004)
- [j24]Kanak Agarwal, Dennis Sylvester, David Blaauw: A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1346-1354 (2004)
- [j23]Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Postroute gate sizing for crosstalk noise reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1670-1677 (2004)
- [j22]Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 131-139 (2004)
- [j21]Dongwoo Lee, David Blaauw, Dennis Sylvester: Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 155-166 (2004)
- [j20]Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans. VLSI Syst. 12(2): 167-184 (2004)
- [c89]Kanak Agarwal, Dennis Sylvester, David Blaauw: A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. ASP-DAC 2004: 858-864
- [c88]Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: A stochastic approach To power grid analysis. DAC 2004: 171-176
- [c87]Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge: Circuit-aware architectural simulation. DAC 2004: 305-310
- [c86]Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384
- [c85]Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Parametric yield estimation considering leakage variability. DAC 2004: 442-447
- [c84]Aseem Agarwal, Florentin Dartu, David Blaauw: Statistical gate delay model considering multiple input switching. DAC 2004: 658-663
- [c83]Dongwoo Lee, Vladimir Zolotov, David Blaauw: Static timing analysis using backward signal propagation. DAC 2004: 664-669
- [c82]Ashish Srivastava, Dennis Sylvester, David Blaauw: Statistical optimization of leakage power considering process variations using dual-Vth and sizing. DAC 2004: 773-778
- [c81]Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw: Leakage-and crosstalk-aware bus encoding for total power reduction. DAC 2004: 779-782
- [c80]Ashish Srivastava, Dennis Sylvester, David Blaauw: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. DAC 2004: 783-787
- [c79]Bo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner: Theoretical and practical limits of dynamic voltage scaling. DAC 2004: 868-873
- [c78]Dongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. DATE 2004: 494-499
- [c77]Ashish Srivastava, Dennis Sylvester, David Blaauw: Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. DATE 2004: 718-719
- [c76]Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge: Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED 2004: 319-324
- [c75]Woo Hyung Lee, Sanjay Pant, David Blaauw: Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. ISQED 2004: 131-136
- [c74]Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner: Extended dynamic voltage scaling for low power design. SoCC 2004: 389-394
- 2003
- [j19]Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan: Leakage Current: Moore's Law Meets Static Power. IEEE Computer 36(12): 68-75 (2003)
- [j18]Rajendran Panda, Savithri Sundareswaran, David Blaauw: Impact of Low-Impedance Substrate on Power Supply Integrity. IEEE Design & Test of Computers 20(3): 16-22 (2003)
- [j17]David Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta: Static electromigration analysis for on-chip signal interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 39-48 (2003)
- [j16]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003)
- [j15]Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj: Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 337-345 (2003)
- [j14]Li Ding, David T. Blaauw, Pinaki Mazumder: Accurate crosstalk noise modeling for early signal integrity analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 627-634 (2003)
- [j13]David T. Blaauw, Luciano Lavagno: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 962-963 (2003)
- [j12]Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul: Probabilistic analysis of interconnect coupling noise. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1188-1203 (2003)
- [j11]Aseem Agarwal, Vladimir Zolotov, David T. Blaauw: Statistical timing analysis using bounds and selective enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1243-1260 (2003)
- [j10]David Blaauw, Supamas Sirichotiyakul, Chanhee Oh: Driver modeling and alignment for worst-case delay noise. IEEE Trans. VLSI Syst. 11(2): 157-166 (2003)
- [c73]Aseem Agarwal, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda: Statistical delay computation considering spatial correlations. ASP-DAC 2003: 271-276
- [c72]Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang: Reshaping EDA for power. DAC 2003: 15
- [c71]Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Analysis and minimization techniques for total leakage considering gate oxide leakage. DAC 2003: 175-180
- [c70]Dongwoo Lee, David Blaauw: Static leakage reduction through simultaneous threshold voltage and state assignment. DAC 2003: 191-194
- [c69]Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Computation and Refinement of Statistical Bounds on Circuit Delay. DAC 2003: 348-353
- [c68]Kanak Agarwal, Dennis Sylvester, David Blaauw: An effective capacitance based driver output model for on-chip RLC interconnects. DAC 2003: 376-381
- [c67]Bhavana Thudi, David Blaauw: Non-iterative switching window computation for delay-noise. DAC 2003: 390-395
- [c66]Kanak Agarwal, Dennis Sylvester, David Blaauw: Simple metrics for slew rate of RC circuits based on two circuit moments. DAC 2003: 950-953
- [c65]Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-route gate sizing for crosstalk noise reduction. DAC 2003: 954-957
- [c64]Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical Timing Analysis Using Bounds. DATE 2003: 10062-10067
- [c63]Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD 2003: 184-192
- [c62]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: AU: Timing Analysis Under Uncertainty. ICCAD 2003: 615-620
- [c61]Nam Sung Kim, David Blaauw, Trevor N. Mudge: Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. ICCAD 2003: 627-632
- [c60]Aseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. ICCAD 2003: 900-907
- [c59]Aseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Clock Skew Analysis Considering Intra-Die Process Variations. ICCAD 2003: 914-921
- [c58]D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel: SOI Transistor Model for Fast Transient Simulation. ICCAD 2003: 120128
- [c57]Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester: Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264-
- [c56]Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671
- [c55]Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical estimation of leakage current considering inter- and intra-die process variation. ISLPED 2003: 84-89
- [c54]Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED 2003: 171-176
- [c53]Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. ISQED 2003: 287-292
- [c52]Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta: Static Electromigration Analysis for Signal Interconnects. ISQED 2003: 377-
- [c51]Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw: An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ISVLSI 2003: 149-154
- [c50]Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18
- 2002
- [j9]David Blaauw, Luciano Lavagno: Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference. IEEE Design & Test of Computers 19(4): 72-73 (2002)
- [j8]David Blaauw, Steven M. Martin, Trevor N. Mudge, Krisztián Flautner: Leakage Current Reduction in VLSI Systems. Journal of Circuits, Systems, and Computers 11(6): 621-636 (2002)
- [j7]Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw: Hierarchical analysis of power distribution networks. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 159-168 (2002)
- [j6]David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran: Slope propagation in static timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1180-1195 (2002)
- [j5]Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov: False-noise analysis using logic implications. ACM Trans. Design Autom. Electr. Syst. 7(3): 474-498 (2002)
- [j4]Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw: Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. IEEE Trans. VLSI Syst. 10(2): 79-90 (2002)
- [j3]Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi: Inductance model and analysis methodology for high-speed on-chip interconnect. IEEE Trans. VLSI Syst. 10(6): 730-745 (2002)
- [c49]Sarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul: Estimation of the likelihood of capacitive coupling noise. DAC 2002: 653-658
- [c48]Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj: Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE 2002: 456-463
- [c47]Himanshu Kaul, Dennis Sylvester, David Blaauw: Active shields: a new approach to shielding global wires. ACM Great Lakes Symposium on VLSI 2002: 112-117
- [c46]Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227
- [c45]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Estimation of signal arrival times in the presence of delay noise. ICCAD 2002: 418-422
- [c44]Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy: Noise propagation and failure criteria for VLSI designs. ICCAD 2002: 587-594
- [c43]Li Ding, David Blaauw, Pinaki Mazumder: Efficient crosstalk noise modeling using aggressor and tree reductions. ICCAD 2002: 595-600
- [c42]Steven M. Martin, Krisztián Flautner, Trevor N. Mudge, David Blaauw: Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. ICCAD 2002: 721-725
- [c41]Krisztián Flautner, Nam Sung Kim, Steven M. Martin, David Blaauw, Trevor N. Mudge: Drowsy Caches: Simple Techniques for Reducing Leakage Power. ISCA 2002: 148-157
- [c40]Li Ding, Pinaki Mazumder, David Blaauw: Crosstalk noise estimation using effective coupling capacitance. ISCAS (5) 2002: 645-648
- [c39]Ashish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester: Modeling and analysis of leakage power considering within-die process variations. ISLPED 2002: 64-67
- [c38]Murat R. Becer, Rajendran Panda, David Blaauw, Ibrahim N. Hajj: Pre-route Noise Estimation in Deep Submicron Integrated Circuits. ISQED 2002: 413-418
- [c37]Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh: Noise Injection and Propagation in High Performance Designs. ISQED 2002: 425-430
- [c36]Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh: False-Noise Analysis Using Resolution Method. ISQED 2002: 437-
- [c35]Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. MICRO 2002: 219-230
- [c34]Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David Blaauw: Robust SAT-Based Search Algorithm for Leakage Power Reduction. PATMOS 2002: 167-177
- [c33]Murat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda: Early probabilistic noise estimation for capacitively coupled interconnects. SLIP 2002: 77-83
- [c32]Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 16-21
- [c31]Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 29-36
- [c30]Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driving point model for on-chip RLC interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69
- [c29]Bhavana Thudi, David Blaauw: Efficient switching window computation for cross-talk noise. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 84-91
- [c28]Himanshu Kaul, Dennis Sylvester, David Blaauw: Active shielding of RLC global interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 98-104
- 2001
- [c27]Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao: Inductance 101: Analysis and Design Issues. DAC 2001: 329-334
- [c26]Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo: Driver Modeling and Alignment for Worst-Case Delay Noise. DAC 2001: 720-725
- [c25]Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov: False-Noise Analysis using Logic Implications. ICCAD 2001: 515-
- [c24]Rajendran Panda, Savithri Sundareswaran, David Blaauw: On the interaction of power distribution network with substrate. ISLPED 2001: 388-393
- [c23]
- [c22]Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj: A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ISQED 2001: 158-
- 2000
- [c21]Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw: On-chip inductance modeling and analysis. DAC 2000: 63-68
- [c20]Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw: Hierarchical analysis of power distribution networks. DAC 2000: 150-155
- [c19]Rajat Chaudhry, David Blaauw, Rajendran Panda, Tim Edwards: Current signature compression for IR-drop analysis. DAC 2000: 162-167
- [c18]Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov: ClariNet: a noise analysis tool for deep submicron design. DAC 2000: 233-238
- [c17]David Blaauw, Rajendran Panda, Abhijit Das: Removing user specified false paths from timing graphs. DAC 2000: 270-273
- [c16]David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang: On-chip inductance modeling. ACM Great Lakes Symposium on VLSI 2000: 75-80
- [c15]David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda: Slope Propagation in Static Timing Analysis. ICCAD 2000: 338-343
- [c14]Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju: Model and analysis for combined package and on-chip power grid simulation. ISLPED 2000: 179-184
- [c13]Rajat Chaudhry, Rajendran Panda, Tim Edwards, David Blaauw: Design and Analysis of Power Distribution Networks with Accurate RLC Models. VLSI Design 2000: 151-155
- [e2]David Blaauw, Christian C. Enz, Thaddeus Gabara, Enrico Macii (Eds.): Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000. ACM 2000, ISBN 1-58113-190-9
1990 – 1999
- 1999
- [c12]Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw: Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC 1999: 436-441
- [c11]Savithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury: A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. VLSI Design 1999: 175-180
- [e1]Farid N. Najm, Jason Cong, David Blaauw (Eds.): Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999. ACM 1999, ISBN 1-58113-133-X
- 1998
- [c10]Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw: Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC 1998: 388-391
- [c9]Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden: Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC 1998: 738-743
- [c8]David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards: Emerging power management tools for processor design. ISLPED 1998: 143-148
- 1997
- [c7]Sergey Gavrilov, Alexey Glebov, S. Rusakov, David Blaauw, Larry G. Jones, Gopalakrishnan Vijayan: Fast power loss calculation for digital static CMOS circuits. ED&TC 1997: 411-415
- [c6]Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw: Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662
- [c5]Abhijit Dharchoudhury, David Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning: Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD 1997: 143-148
- 1995
- [c4]Alexey Glebov, David Blaauw, Larry G. Jones: Transistor reordering for low power CMOS gates using an SP-BDD representation. ISLPD 1995: 161-166
- 1994
- [j2]Larry G. Jones, David Blaauw: A cache-based method for accelerating switch-level simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 211-218 (1994)
- 1990
- [j1]Daniel G. Saab, Robert B. Mueller-Thuns, David Blaauw, Joseph T. Rahmeh, Jacob A. Abraham: Hierarchical multi-level fault simulation of large systems. J. Electronic Testing 1(2): 139-149 (1990)
- [c3]David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham: Derivation of signal flow for switch-level simulation. EURO-DAC 1990: 301-305
- [c2]David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham: SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD 1990: 66-69
1980 – 1989
- 1989
- [c1]David Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh: Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC 1989: 179-184
Coauthor Index