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Eduardo I. Boemo
2000 – 2009
- 2008
[c16]David M. Cambre, Eduardo I. Boemo, Elias Todorovich: Arithmetic Operations and Their Energy Consumption in the Nios II Embedded Processor. ReConFig 2008: 151-156- 2006
- [c15]J. Gonzalez-Gomez, Ivan Gonzalez, Francisco J. Gomez-Arribas, Eduardo I. Boemo: Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors. ARC 2006: 24-29
- [c14]
- 2005
- [c13]J. Gonzalez-Gomez, Eduardo I. Boemo: Motion of Minimal Configurations of a Modular Robot: Sinusoidal, Lateral Rolling and Lateral Shift. CLAWAR 2005: 667-674
- [c12]Elias Todorovich, Fabian Angarita, Javier Valls, Eduardo I. Boemo: Statistical Power Estimation for FPGA. FPL 2005: 515-518
- 2004
- [c11]Sergio López-Buedo, Eduardo I. Boemo: Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report. FPGA 2004: 79-86
- [c10]Elias Todorovich, Eduardo I. Boemo, F. Cardells, Javier Valls: Power analysis and estimation tool integrated with XPOWER. FPGA 2004: 259
- [c9]Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo: Power Aware Dividers in FPGA. PATMOS 2004: 574-584
- [i1]C. M. Gonzalez, Hilda A. Larrondo, C. A. Gayoso, Leonardo J. Arnone, Eduardo I. Boemo: Digital Signal Transmission with Chaotic Encryption: Design and Evaluation of a FPGA Realization. CoRR cs.CR/0402056 (2004)
- 2002
- [c8]Sergio López-Buedo, Paula Riviere, Pablo Pernas, Eduardo I. Boemo: Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology. FPL 2002: 162-170
- [c7]Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo: A Tool for Activity Estimation in FPGAs. FPL 2002: 340-349
- [c6]Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo: FSM Decomposition for Low Power in FPGA. FPL 2002: 350-359
- [c5]Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo: Low-Power FSMs in FPGA: Encoding Alternatives. PATMOS 2002: 363-370
- 2000
- [j2]Sergio López-Buedo, Javier Garrido, Eduardo I. Boemo: Thermal Testing on Reconfigurable Computers. IEEE Design & Test of Computers 17(1): 84-91 (2000)
1990 – 1999
- 1999
- [c4]Javier Valls, T. Sansaloni, M. M. Peiro, Eduardo I. Boemo: Fast FPGA-based pipelined digit-serial/parallel multipliers. ISCAS (1) 1999: 482-485
- 1998
- [j1]Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses: Some experiments about wave pipelining on FPGA's. IEEE Trans. VLSI Syst. 6(2): 232-237 (1998)
- 1997
- [c3]Eduardo I. Boemo, Sergio López-Buedo: Thermal monitoring on FPGAs using ring-oscillators. FPL 1997: 69-78
- 1996
- [c2]Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses: The Wave Pipeline Effect on LUT-Based FPGA Architectures. FPGA 1996: 45-50
- 1995
- [c1]Eduardo I. Boemo, Guillermo González de Rivera, Sergio López-Buedo, Juan M. Meneses: Some Notes on Power Management on FPGA-Based Systems. FPL 1995: 149-157
Coauthor Index
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last updated on 2013-05-24 22:22 CEST by the dblp team