S. Wayne Bollinger

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	1996
j3		John Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit DasGupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang: Design planning for high-performance ASICs. IBM Journal of Research and Development 40(4): 431-452 (1996)
	1994
j2		S. Wayne Bollinger, Scott F. Midkiff: Test generation for I_DDQ testing of bridging faults in CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(11): 1413-1418 (1994)
	1991
j1		S. Wayne Bollinger, Scott F. Midkiff: Heuristic Technique for Processor and Link Assignment in Multicomputers. IEEE Trans. Computers 40(3): 325-333 (1991)
c2		S. Wayne Bollinger, Scott F. Midkiff: On Test Generation for Iddq Testing of Bridging Faults in CMOS Circuits. ITC 1991: 598-607
	1988
c1		S. Wayne Bollinger, Scott F. Midkiff: Processor and Link Assignment in Multicomputers Using Simulated Annealing. ICPP (1) 1988: 1-7

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