Leticia Maria Veiras Bolzani

Leticia Maria Veiras Bolzani Poehls

	2011
j3		Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt, Leticia Maria Veiras Bolzani Poehls, Fabian Vargas, Yervant Zorian: 12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. J. Low Power Electronics 7(4): 529-530 (2011)
c20		Dhiego Silva, K. Stangherlin, Leticia Maria Veiras Bolzani, Fabian Vargas: A Hardware-Based Approach for Fault Detection in RTOS-Based Embedded Systems. European Test Symposium 2011: 209
c19		Dhiego Silva, Leticia Maria Veiras Bolzani, Fabian Vargas: An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systems. IOLTS 2011: 19-24
	2010
j2		Paolo Bernardi, Leticia Maria Veiras Bolzani Poehls, Michelangelo Grosso, Matteo Sonza Reorda: A Hybrid Approach for Detection and Correction of Transient Faults in SoCs. IEEE Trans. Dependable Sec. Comput. 7(4): 439-445 (2010)
c18		F. Lavratti, Alex R. Pinto, Leticia Maria Veiras Bolzani, Fabian Vargas, Carlos B. Montez, Fernando Hernandez, Edmundo Gatti, C. Silva: Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments. DSD 2010: 509-515
c17		Raul Chipana, Leticia Maria Veiras Bolzani, Fabian Vargas, Jorge Semião, Juan J. Rodríguez-Andina, Isabel C. Teixeira, Paulo J. Teixeira: Investigating the Use of BICS to detect resistive-open defects in SRAMs. IOLTS 2010: 200-201
	2009
c16		Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino: Enabling concurrent clock and power gating in an industrial design flow. DATE 2009: 334-339
c15		Jimmy Tarrillo, Leticia Maria Veiras Bolzani Poehls, Fabian Vargas: A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems. DSD 2009: 341-347
c14		Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino: Placement-aware Clustering for Integrated Clock and Power Gating. ISCAS 2009: 1723-1726
	2008
c13		Enrico Macii, Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino: Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. DSD 2008: 298-303
	2007
c12		Leticia Maria Veiras Bolzani, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero: Co-evolution of test programs and stimuli vectors for testing of embedded peripheral cores. IEEE Congress on Evolutionary Computation 2007: 3474-3481
c11		Paolo Bernardi, Leticia Maria Veiras Bolzani, Matteo Sonza Reorda: Extended Fault Detection Techniques for Systems-on-Chip. DDECS 2007: 55-60
c10		Leticia Maria Veiras Bolzani, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero: Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores. GECCO 2007: 1912-1919
c9		Paolo Bernardi, Leticia Maria Veiras Bolzani, Matteo Sonza Reorda: A Hybrid Approach to Fault Detection and Correction in SoCs. IOLTS 2007: 107-112
c8		Leticia Maria Veiras Bolzani, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero: An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores. IOLTS 2007: 265-270
c7		Leticia Maria Veiras Bolzani, Paolo Bernardi, Matteo Sonza Reorda: An optimized hybrid approach to provide fault detection and correction in SoCs. SBCCI 2007: 342-347
c6		Leticia Maria Veiras Bolzani, Edgar E. Sánchez, Matteo Sonza Reorda: A software-based methodology for the generation of peripheral test sets based on high-level descriptions. SBCCI 2007: 348-353
	2006
j1		Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: A New Hybrid Fault Detection Technique for Systems-on-a-Chip. IEEE Trans. Computers 55(2): 185-198 (2006)
c5		Paolo Bernardi, Leticia Maria Veiras Bolzani, Alberto Manzone, Marcella Guagliumi Massimo Osella, Massimo Violante, Matteo Sonza Reorda: Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. MTV 2006: 3-8
	2005
c4		Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. DFT 2005: 445-453
c3		Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. DSN 2005: 50-58
	2004
c2		Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: Hybrid Soft Error Detection by Means of Infrastructure IP Cores. IOLTS 2004: 79-88
	2003
c1		Fabian Vargas, Diogo B. Brum, Dárcio Prestes, Leticia Maria Veiras Bolzani, Eduardo Luis Rhod, Matteo Sonza Reorda: Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy? IOLTS 2003: 163

Coauthor Index

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