Tomasz Borejko

Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz: LC-VCO design automation tool for nanometer CMOS technology. DDECS 2012: 68-73

Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz: PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications. DDECS 2011: 29-34

Michal Lukaszewicz, Tomasz Borejko, Witold A. Pleskacz: A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations. DDECS 2011: 75-79

Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz: CAD tool for PLL Design. DDECS 2011: 283-286

Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz: A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies. DDECS 2010: 213-216

Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz: Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS. DDECS 2009: 78-83

Witold A. Pleskacz, Viera Stopjaková, Tomasz Borejko, Artur Jutman, Andrzej Wakanis: DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits. IEEE Transactions on Industrial Electronics 55(6): 2405-2415 (2008)

Tomasz Borejko, Witold A. Pleskacz: A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations. DDECS 2008: 38-43

Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková: Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. DDECS 2008: 259-262

Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz: CMOS Standard Cells Characterization for IDDQ Testing. DFT 2002: 390-398