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Dominique Borrione
2010 – today
- 2010
[j10]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic: Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1436-1448 (2010)
2000 – 2009
- 2009
- [j9]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz: A Formal Approach to the Verification of Networks on Chip. EURASIP J. Emb. Sys. 2009 (2009)
- [c43]Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre: High-level symbolic simulation for automatic model extraction. DDECS 2009: 218-221
- [c42]Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic: MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI 2009: 75-80
- [c41]Yann Oddos, Katell Morin-Allory, Dominique Borrione: From Assertion-Based Verification to Assertion-Based Synthesis. VLSI-SoC 2009: 94-117
- 2008
- [j8]Julien Schmaltz, Dominique Borrione: A functional formalization of on chip communications. Formal Asp. Comput. 20(3): 241-258 (2008)
- [c40]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic: Proving and disproving assertion rewrite rules with automated theorem provers. HLDVT 2008: 56-63
- [c39]Yann Oddos, Katell Morin-Allory, Dominique Borrione: Assertion-Based Design with Horus. MEMOCODE 2008: 75-76
- [c38]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz: Executable formal specification and validation of NoC communication infrastructures. SBCCI 2008: 176-181
- 2007
- [j7]Katell Morin-Allory, Eric Gascard, Dominique Borrione: Synthesis of Property Monitors for Online Fault Detection. Journal of Circuits, Systems, and Computers 16(6): 943-960 (2007)
- [c37]Yann Oddos, Katell Morin-Allory, Dominique Borrione: Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. DDECS 2007: 383-388
- [c36]Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione: Asynchronous online-monitoring of logical and temporal assertions. FDL 2007: 286-290
- [c35]Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz: A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. NOCS 2007: 127-136
- 2006
- [c34]Julien Schmaltz, Dominique Borrione: Towards a formal theory of on chip communications in the ACL2 logic. ACL2 2006: 47-56
- [c33]Julien Schmaltz, Dominique Borrione: Formalizing On Chip Communications in a Functional Style. Trustworthy Software 2006
- [c32]Katell Morin-Allory, Dominique Borrione: Proven correct monitors from PSL specifications. DATE 2006: 1246-1251
- [c31]Katell Morin-Allory, Dominique Borrione: On-line Monitoring of Properties Built on Regular Expressions. FDL 2006: 249-255
- [c30]Katell Morin-Allory, Laurent Fesquet, Dominique Borrione: Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping 2006: 98-102
- [c29]Yann Oddos, Katell Morin-Allory, Dominique Borrione: On-Line Test Vector Generation from Temporal Constraints Written in PSL. VLSI-SoC 2006: 397-402
- 2005
- [c28]Ghiath Al Sammane, Dominique Borrione, Remy Chevallier: Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. ACM Great Lakes Symposium on VLSI 2005: 260-263
- [c27]Katell Morin-Allory, Dominique Borrione: A proof of correctness for the construction of property monitors. HLDVT 2005: 237-244
- [c26]
- [c25]Diana Toma, Dominique Borrione: Formal Verification of a SHA-1 Circuit Core Using ACL2. TPHOLs 2005: 326-341
- [e1]Dominique Borrione, Wolfgang J. Paul (Eds.): Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings. Lecture Notes in Computer Science 3725, Springer 2005, ISBN 3-540-29105-9
- 2004
- [c24]Diana Toma, Dominique Borrione, Ghiath Al Sammane: Combining Several Paradigms for Circuit Validation and Verification. CASSIS 2004: 229-249
- [c23]Julien Schmaltz, Dominique Borrione: A Functional Approach to the Formal Specification of Networks on Chip. FMCAD 2004: 52-66
- [c22]Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione: TheoSim: combining symbolic simulation and theorem proving for hardware verification. SBCCI 2004: 60-65
- 2003
- [c21]Ghiath Al Sammane, Diana Toma, Julien Schmaltz, Pierre Ostier, Dominique Borrione: Constrained Symbolic Simulation with Mathematica and ACL2. CHARME 2003: 150-157
- [c20]Dominique Borrione, Menouer Boubekeur: Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications. FDL 2003: 481-492
- [c19]Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Sirianni: An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS 2003: 279
- [c18]Emil Dumitrescu, Dominique Borrione: Symbolic Simulation as a Simplifying Strategy for SoC Verification. IWSOC 2003: 378-383
- [c17]Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Sirianni: Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC 2003: 86-91
- 2002
- [c16]Joel Blasquez, Marten van Hulst, Andrea Fedeli, Jean-Luc Lambert, Dominique Borrione, Coby Hanoch, Pierre Bricaud: Formal Verification Techniques: Industrial Status and Perspectives. DATE 2002: 1050
- [c15]Jorgiano Vidal, David Déharbe, Dominique Borrione: Improving Static Ordering of BDDs for Reachability Analysis. IWLS 2002: 73-77
- 2001
- [c14]S. Reda, Ayman M. Wahba, Ashraf M. Salem, Dominique Borrione, M. Ghonaimy: On the use of don't cares during symbolic reachability analysis. ISCAS (5) 2001: 121-124
- 2000
- [j6]Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin: Using the ACL2 Theorem Prover to Reason about VHDL Components. RITA 7(1): 129-148 (2000)
- [j5]Dominique Borrione, Julia Dushina, Laurence V. Pierre: A compositional model for the functional verification of high-level synthesis results. IEEE Trans. VLSI Syst. 8(5): 526-530 (2000)
1990 – 1999
- 1999
- [c13]Raimund Ubar, Dominique Borrione: Design Error Diagnosis in Digital Circuits without Error Model. VLSI 1999: 281-292
- 1997
- [c12]Dominique Borrione, F. Vestman, H. Bouamama: An approach to Verilog-VHDL interoperability for synchronous designs. CHARME 1997: 65-87
- [c11]Ayman M. Wahba, Dominique Borrione: Connection error location and correction in combinational circuits. ED&TC 1997: 235-241
- 1996
- [j4]Ayman M. Wahba, Dominique Borrione: A method for automatic design error location and correction in combinational logic circuits. J. Electronic Testing 8(2): 113-127 (1996)
- [c10]Dominique Borrione, H. Bouamama, David Déharbe, C. Le Faou, Ayman M. Wahba: HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment. FMCAD 1996: 450-467
- 1995
- [j3]Dominique Borrione, Ashraf M. Salem: Denotational Semantics of a Synchronous VHDL Subset. Formal Methods in System Design 7(1/2): 53-71 (1995)
- [c9]Ayman M. Wahba, Dominique Borrione: Design error diagnosis in sequential circuits. CHARME 1995: 171-188
- [c8]David Déharbe, Dominique Borrione: Semantics of a verification-oriented subset of VHDL. CHARME 1995: 293-310
- 1994
- [c7]Catherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto: A process algebra interpretation of a verification oriented overlanguage of VHDL. EURO-DAC 1994: 506-511
- 1992
- [j2]Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem: Formal Verification of VHDL Descriptions in the Prevail Environment. IEEE Design & Test of Computers 9(2): 42-56 (1992)
- [j1]Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby: Three Decades of HDLs: Part II, Conlan Through Verilog. IEEE Design & Test of Computers 9(3): 54-63 (1992)
1980 – 1989
- 1989
- [c6]Dominique Borrione, Paolo Prinetto: Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis. IFIP Congress 1989: 233-240
- 1983
- [b1]Robert Piloty, Dominique Borrione, Mario Barbacci, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN Report. Lecture Notes in Computer Science 151, Springer 1983, ISBN 3-540-12275-3
- 1982
- [c5]
- 1980
- [c4]Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN: a formal construction method for hardware description languages: basic principles. AFIPS National Computer Conference 1980: 209-217
- [c3]Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN: a formal construction method for hardware description languages: language derivation. AFIPS National Computer Conference 1980: 219-227
- [c2]Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN: a formal construction method for hardware description languages: language application. AFIPS National Computer Conference 1980: 229-236
- [c1]Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: An Overview of CONLAN: A Formal Construction Method for Hardware Description Language. IFIP Congress 1980: 199-204
Coauthor Index
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last updated on 2012-12-02 21:21 CET by the dblp team