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 | 2007 | |
|---|---|---|
| c14 |      | Soumitra Bose, Vishwani D. Agrawal: Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. ITC 2007: 1-10 |
| c13 | | Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal: Delay fault simulation with bounded gate delay mode. ITC 2007: 1-10 |
| c12 | | Soumitra Bose, Vishwani D. Agrawal: Delay Test Quality Evaluation Using Bounded Gate Delays. VTS 2007: 23-28 |
| 2006 | ||
| c11 | | Soumitra Bose, Vishwani D. Agrawal: Fault Coverage Estimation for Non-Random Functional Input Sequences. ITC 2006: 1-10 |
| c10 | | Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram: Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. VTS 2006: 88-93 |
| 2005 | ||
| j6 | | Soumitra Bose, Amit Nandi: Schematic array models for associative and non-associative memory circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1582-1593 (2005) |
| 2004 | ||
| j5 | | Soumitra Bose: Modeling Custom Digital Circuits for Test. J. Electronic Testing 20(6): 591-609 (2004) |
| c9 | | Soumitra Bose, Amit Nandi: Extraction of Schematic Array Models for Memory Circuits. DATE 2004: 570-577 |
| 2002 | ||
| c8 | | |
| 1998 | ||
| j4 | | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Deriving Logic Systems for Path Delay Test Generation. IEEE Trans. Computers 47(8): 829-846 (1998) |
| 1997 | ||
| c7 | | Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski: Algorithms for Switch Level Delay Fault Simulation. ITC 1997: 982-991 |
| 1995 | ||
| c6 | | Soumitra Bose, Vishwani D. Agrawal: Sequential logic path delay test generation by symbolic analysis. Asian Test Symposium 1995: 353- |
| 1993 | ||
| j3 | | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: The optimistic update theorem for path delay testing in sequential circuits. J. Electronic Testing 4(3): 285-290 (1993) |
| j2 | | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Path delay fault simulation of sequential circuits. IEEE Trans. VLSI Syst. 1(4): 453-461 (1993) |
| c5 | | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Generation of Compact Delay Tests by Multiple-Path Activation. ITC 1993: 714-723 |
| c4 |  | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: A Path Delay Fault Simulator for Sequential Circuits. VLSI Design 1993: 269-274 |
| 1992 | ||
| j1 | | Soumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov: PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. J. Autom. Reasoning 8(2): 153-181 (1992) |
| c3 | | Soumitra Bose, Prathima Agrawal: Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers. DAC 1992: 332-335 |
| 1989 | ||
| c2 | | Soumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov: PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. LICS 1989: 80-89 |
| 1988 | ||
| c1 | | P. E. Allen, Soumitra Bose, Edmund M. Clarke, Spiro Michaylov: PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. CADE 1988: 764-765 |
| 1 | Prathima Agrawal | |
| 2 | Vishwani D. Agrawal | |
| 3 | P. E. Allen | |
| 4 | Edmund M. Clarke | |
| 5 | Vijay Gangaram | |
| 6 | Hillary Grimes | |
| 7 | David E. Long | |
| 8 | Spiro Michaylov | |
| 9 | Amit Nandi | |
| 10 | Thomas G. Szymanski |
Colors in the list of coauthors
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