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 | 2010 | |
|---|---|---|
| j5 |      | Jason G. Tong, Marc Boule, Zeljko Zilic: Defining and Providing Coverage for Assertion-Based Dynamic Verification. J. Electronic Testing 26(2): 211-225 (2010) |
| j4 | | Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic: Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1436-1448 (2010) |
| 2009 | ||
| c8 | | Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic: MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI 2009: 75-80 |
| c7 | | Jason G. Tong, Marc Boule, Zeljko Zilic: Airwolf-TG: A test generator for assertion-based dynamic verification. HLDVT 2009: 106-113 |
| 2008 | ||
| j3 | | Marc Boule, Zeljko Zilic: Automata-based assertion-checker synthesis of PSL properties. ACM Trans. Design Autom. Electr. Syst. 13(1) (2008) |
| c6 | | Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic: Proving and disproving assertion rewrite rules with automated theorem provers. HLDVT 2008: 56-63 |
| 2007 | ||
| j2 | | Marc Boule, Jean-Samuel Chenard, Zeljko Zilic: Debug enhancements in assertion-checker generation. IET Computers & Digital Techniques 1(6): 669-677 (2007) |
| c5 | | Marc Boule, Zeljko Zilic: Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. ASP-DAC 2007: 324-329 |
| c4 | | Marc Boule, Jean-Samuel Chenard, Zeljko Zilic: Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. ISQED 2007: 613-620 |
| 2006 | ||
| c3 | | Marc Boule, Zeljko Zilic: Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties. HLDVT 2006: 69-76 |
| c2 | | Marc Boule, Jean-Samuel Chenard, Zeljko Zilic: Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. ICCD 2006 |
| 2005 | ||
| c1 | | Marc Boule, Zeljko Zilic: Incorporating Ef.cient Assertion Checkers into Hardware Emulation. ICCD 2005: 221-228 |
| 2002 | ||
| j1 |  | Marc Boule, Zeljko Zilic: An FPGA Move Generator for the Game of Chess. ICGA Journal 25(2): 85-94 (2002) |
| 1 | Dominique Borrione | |
| 2 | Jean-Samuel Chenard | |
| 3 | Katell Morin-Allory | |
| 4 | Yann Oddos | |
| 5 | Jason G. Tong | |
| 6 | Zeljko Zilic |
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