Eli Bozorgzadeh
List of publications from the DBLP Bibliography Server - FAQ| 2012 | ||
|---|---|---|
| j21 | Nga Dang, Elaheh Bozorgzadeh, Nalini Venkatasubramanian: Energy Harvesting for Sustainable Smart Spaces. Advances in Computers 87: 203-251 (2012) | |
| j20 | Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh: Hardware-Assisted Detection of Malicious Software in Embedded Systems. Embedded Systems Letters 4(4): 94-97 (2012) | |
| c46 | Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh: Minimization of Trojan footprint by reducing Delay/Area impact. DFT 2012: 59-62 | |
| c45 | Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh: Adaptable intrusion detection using partial runtime reconfiguration. ICCD 2012: 147-152 | |
| c44 | Hessam Kooti, Nga Dang, Deepak Mishra, Eli Bozorgzadeh: Energy Budget Management for Energy Harvesting Embedded Systems. RTCSA 2012: 320-329 | |
| 2011 | ||
| j19 | Aravind Dasu, João M. P. Cardoso, Eli Bozorgzadeh, Jürgen Becker: Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010). Int. J. Reconfig. Comp. 2011 (2011) | |
| j18 | Shahin Golshan, Hessam Kooti, Elaheh Bozorgzadeh: SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(6): 829-840 (2011) | |
| c43 | Hessam Kooti, Deepak Mishra, Eli Bozorgzadeh: Reconfiguration-aware real-time scheduling under QoS constraint. ASP-DAC 2011: 141-146 | |
| c42 | Shahin Golshan, Amin Khajeh, Houman Homayoun, Eli Bozorgzadeh, Ahmed M. Eltawil, Fadi J. Kurdahi: Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations. CODES+ISSS 2011: 257-266 | |
| c41 | Nga Dang, Elaheh Bozorgzadeh, Nalini Venkatasubramanian: QuARES: Quality-aware data collection in energy harvesting sensor networks. IGCC 2011: 1-9 | |
| c40 | Shahin Golshan, Love Singhal, Eli Bozorgzadeh: Process variation aware system-level load assignment for total energy minimization using stochastic ordering. ISQED 2011: 566-571 | |
| 2010 | ||
| j17 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil Dutt: Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures. TRETS 3(3): 18 (2010) | |
| c39 | Hessam Kooti, Elaheh Bozorgzadeh, Shenghui Liao, Lichun Bao: Transition-aware real-time task scheduling for reconfigurable embedded systems. DATE 2010: 232-237 | |
| c38 | Hessam Kooti, Eli Bozorgzadeh: Unified theory of real-time task scheduling and dynamic voltage/frequency Scaling on MPSoCs. ICCAD 2010: 139-142 | |
| c37 | Jürgen Becker, Eli Bozorgzadeh, João M. P. Cardoso, Aravind Dasu: Welcome message. IPDPS Workshops 2010: 1-2 | |
| c36 | Hessam Kooti, Eli Bozorgzadeh, Shenghui Liao, Lichun Bao: Reconfiguration-aware spectrum sharing for FPGA based software defined radio. IPDPS Workshops 2010: 1-4 | |
| c35 | Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum: Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. ISLPED 2010: 49-54 | |
| c34 | Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi: Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks. ISQED 2010: 499-507 | |
| 2009 | ||
| j16 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations. IEEE Trans. VLSI Syst. 17(2): 234-247 (2009) | |
| c33 | Shahin Golshan, Eli Bozorgzadeh: SEU-aware resource binding for modular redundancy based designs on FPGAs. DATE 2009: 1124-1129 | |
| 2008 | ||
| j15 | Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh: Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 409-422 (2008) | |
| c32 | Love Singhal, Sejong Oh, Eli Bozorgzadeh: Statistical power profile correlation for realistic thermal estimation. ASP-DAC 2008: 67-70 | |
| c31 | Love Singhal, Sejong Oh, Eli Bozorgzadeh: Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors. CODES+ISSS 2008: 249-254 | |
| c30 | Love Singhal, Elaheh Bozorgzadeh: Process variation aware system-level task allocation using stochastic ordering of delay distributions. ICCAD 2008: 570-574 | |
| c29 | Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao: Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs. ICCD 2008: 260-265 | |
| 2007 | ||
| j14 | Love Singhal, Elaheh Bozorgzadeh: Multi-layer floorplanning for reconfigurable designs. IET Computers & Digital Techniques 1(4): 276-294 (2007) | |
| j13 | Love Singhal, Elaheh Bozorgzadeh, David Eppstein: Interconnect Criticality-Driven Delay Relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1803-1817 (2007) | |
| c28 | Shahin Golshan, Elaheh Bozorgzadeh: Single-Event-Upset (SEU) Awareness in FPGA Routing. DAC 2007: 330-333 | |
| c27 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera: Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. DAC 2007: 771-776 | |
| c26 | ||
| c25 | Love Singhal, Elaheh Bozorgzadeh: Novel Multi-Layer floorplanning for Heterogeneous FPGAs. FPL 2007: 613-616 | |
| c24 | Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Sudarshan Banerjee: Energy-aware co-processor selection for embedded processors on FPGAs. ICCD 2007: 158-163 | |
| 2006 | ||
| j12 | Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh: Statistical Analysis and Design of HARP FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2088-2102 (2006) | |
| j11 | Soheil Ghiasi, Elaheh Bozorgzadeh, Po-Kuan Huang, Roozbeh Jafari, Majid Sarrafzadeh: A Unified Theory of Timing Budget Management. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2364-2375 (2006) | |
| j10 | Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane: FABSYN: floorplan-aware bus architecture synthesis. IEEE Trans. VLSI Syst. 14(3): 241-253 (2006) | |
| j9 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration. IEEE Trans. VLSI Syst. 14(11): 1189-1202 (2006) | |
| j8 | Soheil Ghiasi, Elaheh Bozorgzadeh, Karlene Nguyen, Majid Sarrafzadeh: Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System. VLSI Signal Processing 42(1): 43-55 (2006) | |
| c23 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt: PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. ASP-DAC 2006: 491-496 | |
| c22 | ||
| c21 | Love Singhal, Elaheh Bozorgzadeh: Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. FPL 2006: 1-8 | |
| c20 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil Dutt: Minimizing peak power for application chains on architectures with partial dynamic reconfiguration. FPT 2006: 273-276 | |
| c19 | Love Singhal, Elaheh Bozorgzadeh: Physically-aware exploitation of component reuse in a partially reconfigurable architecture. IPDPS 2006 | |
| 2005 | ||
| j7 | Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh: A scheduling algorithm for optimization and early planning in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 10(1): 33-57 (2005) | |
| c18 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. DAC 2005: 335-340 | |
| c17 | Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane: Floorplan-aware automated synthesis of bus-based communication architectures. DAC 2005: 565-570 | |
| c16 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures. FCCM 2005: 273-274 | |
| c15 | Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh: HARP: hard-wired routing pattern FPGAs. FPGA 2005: 21-29 | |
| c14 | Love Singhal, Elaheh Bozorgzadeh: Fast timing closure by interconnect criticality driven delay relaxation. ICCAD 2005: 792-797 | |
| 2004 | ||
| j6 | Elaheh Bozorgzadeh, Seda Ogrenci Memik, Xiaojian Yang, Majid Sarrafzadeh: Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs. Journal of Circuits, Systems, and Computers 13(1): 77-100 (2004) | |
| j5 | Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh: Optimal integer delay-budget assignment on directed acyclic graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1184-1199 (2004) | |
| c13 | Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh: Incremental Timing Budget Management in Programmable Systems. ERSA 2004: 240-246 | |
| c12 | Soheil Ghiasi, Elaheh Bozorgzadeh, Siddharth Choudhuri, Majid Sarrafzadeh: A unified theory of timing budget management. ICCAD 2004: 653-659 | |
| 2003 | ||
| j4 | Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh: Creating and exploiting flexibility in rectilinear Steiner trees. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 605-615 (2003) | |
| c11 | Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh: Optimal integer delay budgeting on directed acyclic graphs. DAC 2003: 920-925 | |
| c10 | ||
| c9 | Soheil Ghiasi, Karlene Nguyen, Elaheh Bozorgzadeh, Majid Sarrafzadeh: On computation and resource management in an FPGA-based computation environment. FPGA 2003: 243 | |
| 2002 | ||
| j3 | Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh: Budget Management with Applications. Algorithmica 34(3): 261-275 (2002) | |
| j2 | Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh: Pattern routing: use and theory for increasing predictability andavoiding coupling. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 777-790 (2002) | |
| j1 | Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh: Instruction generation for hybrid reconfigurable systems. ACM Trans. Design Autom. Electr. Syst. 7(4): 605-627 (2002) | |
| 2001 | ||
| c8 | Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh: RPack: routability-driven packing for cluster-based FPGAs. ASP-DAC 2001: 629-634 | |
| c7 | Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh: Creating and Exploiting Flexibility in Steiner Trees. DAC 2001: 195-198 | |
| c6 | Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh: Instruction Generation for Hybrid Reconfigurable Systems. ICCAD 2001: 127- | |
| c5 | Seda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh: A Super-Scheduler for Embedded Reconfigurable Systems. ICCAD 2001: 391- | |
| c4 | Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh: An exact algorithm for coupling-free routing. ISPD 2001: 10-15 | |
| c3 | Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava: Design and analysis of physical design algorithms. ISPD 2001: 82-89 | |
| c2 | Xiaojian Yang, Elaheh Bozorgzadeh, Majid Sarrafzadeh: Wirelength estimation based on rent exponents of partitioning and placement. SLIP 2001: 25-31 | |
| 2000 | ||
| c1 | ||
Colors in the list of coauthors
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