Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Elizabeth J. Brauer
2000 – 2009
- 2009
[j2]Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici: Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP. Microelectronics Journal 40(6): 973-978 (2009)- 2008
- [c12]Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer: Improving the power-delay product in SCL circuits using source follower output stage. ISCAS 2008: 145-148
- [c11]Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici: Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. PATMOS 2008: 21-30
- 2006
- [c10]Elizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici: Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. ISCAS 2006
- [c9]Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer: Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. VLSI-SoC 2006: 234-238
- 2004
- [c8]Elizabeth J. Brauer, Yusuf Leblebici: Low noise MCML prefix adders using 0.18 µm CMOS technology. Circuits, Signals, and Systems 2004: 467-470
- [c7]Elizabeth J. Brauer, Yusuf Leblebici: Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic. Circuits, Signals, and Systems 2004: 483-487
- [c6]Elizabeth J. Brauer, Vikram Magoon: Finding efficient inductor geometries in digital CMOS process for RF applications. Circuits, Signals, and Systems 2004: 558-561
1990 – 1999
- 1997
- [c5]Elizabeth J. Brauer, Pradeep Elamanchili: A Full-Swing Bootstrapped BiCMOS Buffer. Great Lakes Symposium on VLSI 1997: 8-13
- [c4]Elizabeth J. Brauer, Ranu Jung, Denise M. Wilson, James J. Abbas: Analog Circuit Model of Lamprey Unit Pattern Generator. Great Lakes Symposium on VLSI 1997: 137-142
- 1995
- [j1]Elizabeth J. Brauer, Sung-Mo Kang: An algorithm for functional verification of digital ECL circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1546-1556 (1995)
- [c3]Elizabeth J. Brauer, Sung-Mo Kang: Estimating Node Voltages in Bipolar Circuits Using Linear Programming. ISCAS 1995: 901-903
- [c2]Elizabeth J. Brauer, Sung-Mo Kang: An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations. ISCAS 1995: 1580-1583
- 1993
- [c1]Elizabeth J. Brauer, Sung-Mo Kang: Functional Verification of ECL Circuits Including Voltage Regulators. ISCAS 1993: 1710-1713
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2012-12-02 22:19 CET by the dblp team