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Robert K. Brayton

2010 – today

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2013
[c210]
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Alan Mishchenko, Niklas Eén, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma: A semi-canonical form for sequential AIGs. DATE 2013: 797-802
[c209]
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Alan Mishchenko, Niklas Eén, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla: GLA: gate-level abstraction revisited. DATE 2013: 1399-1404
2012
[c208]
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Sayak Ray, Robert K. Brayton: Scalable progress verification in credit-based flow-control systems. DATE 2012: 905-910
[c207]
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Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen: Mapping into LUT structures. DATE 2012: 1579-1584
2011
[j51]
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Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton: Automating Logic Transformations With Approximate SPFDs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(5): 651-664 (2011)
[j50]
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Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang: Scalable don't-care-based logic optimization and resynthesis. TRETS 4(4): 34 (2011)
[c206]
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Niklas Eén, Alan Mishchenko, Robert K. Brayton: Efficient implementation of property directed reachability. FMCAD 2011: 125-134
[c205]
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Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets: Delay optimization using SOP balancing. ICCAD 2011: 375-382
2010
[j49]
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  - journals/dt/BraytonC10
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Robert K. Brayton, Jason Cong: NSF Workshop on EDA: Past, Present, and Future (Part 1). IEEE Design & Test of Computers 27(2): 68-74 (2010)
[j48]
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Robert K. Brayton, Jason Cong: NSF Workshop on EDA: Past, Present, and Future (Part 2). IEEE Design & Test of Computers 27(3): 62-74 (2010)
[c204]
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Robert K. Brayton, Alan Mishchenko: ABC: An Academic Industrial-Strength Verification Tool. CAV 2010: 24-40
[c203]
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Hamid Savoj, David Berthelot, Alan Mishchenko, Robert K. Brayton: Combinational techniques for sequential equivalence checking. FMCAD 2010: 145-149
[c202]
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Alan Mishchenko, Robert K. Brayton, Stephen Jang: Global delay optimization using structural choices. FPGA 2010: 181-184

2000 – 2009

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2009
[c201]
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Hari Mony, Jason Baumgartner, Alan Mishchenko, Robert K. Brayton: Speculative reduction-based scalable redundancy identification. DATE 2009: 1674-1679
[c200]
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Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith: Sequential logic rectifications with approximate SPFDs. DATE 2009: 1698-1703
[c199]
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Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang: Scalable don't-care-based logic optimization and resynthesis. FPGA 2009: 151-160
[c198]
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Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton: SmartOpt: an industrial strength framework for logic synthesis. FPGA 2009: 237-240
2008
[j47]
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Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli: Compositionally Progressive Solutions of Synchronous FSM Equations. Discrete Event Dynamic Systems 18(1): 51-89 (2008)
[c197]
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Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton: Scalable min-register retiming under timing and initializability constraints. DAC 2008: 534-539
[c196]
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Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton: Merging nodes under sequential observability. DAC 2008: 540-545
[c195]
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Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony: Invariant-Strengthened Elimination of Dependent State Elements. FMCAD 2008: 1-9
[c194]
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Alan Mishchenko, Robert K. Brayton: Recording Synthesis History for Sequential Verification. FMCAD 2008: 1-8
[c193]
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Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee: Boolean factoring and decomposition of logic networks. ICCAD 2008: 38-44
[c192]
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Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang: Scalable and scalably-verifiable sequential synthesis. ICCAD 2008: 234-241
[c191]
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Fan Mo, Robert K. Brayton: Placement based multiplier rewiring for cell-based designs. ICCAD 2008: 430-433
2007
[j46]
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Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton: Improvements to Technology Mapping for LUT-Based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 240-253 (2007)
[c190]
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Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton: Automating Logic Rectification by Approximate SPFDs. ASP-DAC 2007: 402-407
[c189]
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Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann: On Resolution Proofs for Combinational Equivalence. DAC 2007: 600-605
[c188]
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Michael L. Case, Alan Mishchenko, Robert K. Brayton: Automated Extraction of Inductive Invariants to Aid Model Checking. FMCAD 2007: 165-172
[c187]
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Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton: Fast Minimum-Register Retiming via Binary Maximum-Flow. FMCAD 2007: 181-187
[c186]
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Tiziano Villa, Svetlana Zharikova, Nina Yevtushenko, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A new algorithm for the largest compositionally progressive solution of synchronous language equations. ACM Great Lakes Symposium on VLSI 2007: 441-444
[c185]
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Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton: Combinational and sequential mapping with priority cuts. ICCAD 2007: 354-361
[c184]
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Fan Mo, Robert K. Brayton: A simultaneous bus orientation and bused pin flipping algorithm. ICCAD 2007: 386-389
[c183]
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Fan Mo, Robert K. Brayton: Semi-detailed bus routing with variation reduction. ISPD 2007: 143-150
[i2]
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Alan Mishchenko, Robert K. Brayton: SAT-Based Complete Don't-Care Computation for Network Optimization. CoRR abs/0710.4695 (2007)
[i1]
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Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko: Efficient Solution of Language Equations Using Partitioned Representations. CoRR abs/0710.4743 (2007)
2006
[j45]
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Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske: Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 743-755 (2006)
[j44]
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Alan Mishchenko, Robert K. Brayton: A theory of nondeterministic networks. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 977-999 (2006)
[j43]
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Jie-Hong Roland Jiang, Robert K. Brayton: Retiming and Resynthesis: A Complexity Perspective. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2674-2686 (2006)
[j42]
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Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam: Reducing Structural Bias in Technology Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2894-2903 (2006)
[c182]
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  - conf/dac/ZhangMBC06
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Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske: Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. DAC 2006: 510-515
[c181]
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Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton: DAG-aware AIG rewriting a fresh look at combinational logic synthesis. DAC 2006: 532-535
[c180]
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Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton: Improvements to technology mapping for LUT-based FPGAs. FPGA 2006: 41-49
[c179]
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Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton: Factor cuts. ICCAD 2006: 143-150
[c178]
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Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén: Improvements to combinational equivalence checking. ICCAD 2006: 836-843
2005
[c177]
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  - conf/acsd/LiKB05
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Yinghua Li, Alex Kondratyev, Robert K. Brayton: Gaining Predictability and Noise Immunity in Global Interconnects. ACSD 2005: 176-185
[c176]
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Alan Mishchenko, Robert K. Brayton: SAT-Based Complete Don't-Care Computation for Network Optimization. DATE 2005: 412-417
[c175]
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Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko: Efficient Solution of Language Equations Using Partitioned Representations. DATE 2005: 418-423
[c174]
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Yinghua Li, Alex Kondratyev, Robert K. Brayton: Synthesis methodology for built-in at-speed testing. ICCAD 2005: 183-188
[c173]
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Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam: Reducing structural bias in technology mapping. ICCAD 2005: 519-526
2004
[j41]
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  - journals/tcad/KhatriSBS04
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Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1020-1030 (2004)
[c172]
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Jie-Hong Roland Jiang, Robert K. Brayton: Functional Dependency for Verification Reduction. CAV 2004: 268-280
[c171]
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Fan Mo, Robert K. Brayton: A timing-driven module-based chip design flow. DAC 2004: 67-70
[c170]
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Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton: On breakable cyclic definitions. ICCAD 2004: 411-418
[c169]
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Satrajit Chatterjee, Robert K. Brayton: A new incremental placement algorithm and its application to congestion-aware divisor extraction. ICCAD 2004: 541-548
2003
[j40]
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Jie-Hong Roland Jiang, Robert K. Brayton: On the verification of sequential equivalence. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 686-697 (2003)
[j39]
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Fan Mo, Robert K. Brayton: PLA-based regular structures and their synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 723-729 (2003)
[j38]
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Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton: Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. 8(2): 222-251 (2003)
[c168]
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Yunjian Jiang, Robert K. Brayton: Don't cares in logic minimization of extended finite state machines. ASP-DAC 2003: 809-815
[c167]
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Yunjian Jiang, Slobodan Matic, Robert K. Brayton: Generalized cofactoring for logic function evaluation. DAC 2003: 155-158
[c166]
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Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton: Reducing Multi-Valued Algebraic Operations to Binary. DATE 2003: 10752-10757
[c165]
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Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli: Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. DATE 2003: 11154-11155
[c164]
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Alan Mishchenko, Robert K. Brayton: A Theory of Non-Deterministic Networks. ICCAD 2003: 709-717
[c163]
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Fan Mo, Robert K. Brayton: Fishbone: a block-level placement and routing scheme. ISPD 2003: 204-209
2002
[j37]
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  - journals/fmsd/AzizSSBS02
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Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Formula-Dependent Equivalence for Compositional CTL Model Checking. Formal Methods in System Design 21(2): 193-224 (2002)
[c162]
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  - conf/codes/BaleaniGJPBS02
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Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. CODES 2002: 151-156
[c161]
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  - conf/dac/MoB02
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Fan Mo, Robert K. Brayton: River PLAs: a regular circuit structure. DAC 2002: 201-206
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Yunjian Jiang, Robert K. Brayton: Software synthesis from synchronous specifications using logic simulation techniques. DAC 2002: 319-324
[c159]
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  - conf/date/GoldbergPB02
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Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton: Using Problem Symmetry in Search Based Satisfiability Algorithms. DATE 2002: 134-141
[c158]
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Fan Mo, Robert K. Brayton: Whirlpool PLAs: a regular logic structure and their synthesis. ICCAD 2002: 543-550
[c157]
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Alan Mishchenko, Robert K. Brayton: Simplification of non-deterministic multi-valued networks. ICCAD 2002: 557-562
[c156]
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  - conf/iccad/SinhaMB02
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Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton: Topologically constrained logic synthesis. ICCAD 2002: 679-686
[c155]
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  - conf/ismvl/BraytonGJJLMSV02
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Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa: Optimization of Multi-Valued Multi-Level Networks. ISMVL 2002: 168-
[c154]
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  dblp key:
  - conf/iwls/MoB02
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Fan Mo, Robert K. Brayton: Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design. IWLS 2002: 7-12
[c153]
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  dblp key:
  - conf/iwls/SinhaMB02
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Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton: Topologically Constrained Logic Synthesis. IWLS 2002: 13-20
[c152]
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  - conf/iwls/YevtushenkoVBPS02
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Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli: Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. IWLS 2002: 45-50
[c151]
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  - conf/iwls/MishchenkoB02
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Alan Mishchenko, Robert K. Brayton: A Boolean Paradigm in Multi-Valued Logic Synthesis. IWLS 2002: 173-177
[c150]
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  dblp key:
  - conf/iwls/JiangB02
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Jie-Hong Roland Jiang, Robert K. Brayton: On the Verification of Sequential Equivalence. IWLS 2002: 307-314
[c149]
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  - conf/iwls/JiangB02a
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Yunjian Jiang, Robert K. Brayton: Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic. IWLS 2002: 327-332
[c148]
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  - conf/iwls/MishchenkoB02a
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Alan Mishchenko, Robert K. Brayton: Simplification of Non-Deterministic Multi-Valued Networks. IWLS 2002: 333-338
[c147]
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  - conf/iwls/JiangMB02
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Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton: Reducing Multi-Valued Algebraic Operations to Binary. IWLS 2002: 339-344
2001
[j36]
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  - journals/fmsd/AlurBHQR01
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Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani: Partial-Order Reduction in Symbolic State-Space Exploration. Formal Methods in System Design 18(2): 97-116 (2001)
[j35]
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  - journals/tcad/SinghalPAB01
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Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton: Theory of safe replacements for sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 249-265 (2001)
[c146]
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  - conf/codes/JiangB01
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Yunjian Jiang, Robert K. Brayton: Logic optimization and code generation for embedded control applications. CODES 2001: 225-229
[c145]
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  - conf/date/GoldbergPB01
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Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton: Using SAT for combinational equivalence checking. DATE 2001: 114-121
[c144]
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  - conf/iccad/SinhaKB01
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Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton: Sequential SPFDs. ICCAD 2001: 84-90
[c143]
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  - conf/iccad/YevtushenkoVBPS01
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Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli: Solution of Parallel Language Equations for Logic Synthesis. ICCAD 2001: 103-
[c142]
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  - conf/iccad/MoTB01
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Fan Mo, Abdallah Tabbara, Robert K. Brayton: A Force-Directed Maze Router. ICCAD 2001: 404-407
[c141]
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Robert K. Brayton: Compatible Observability Don't Cares Revisited. ICCAD 2001: 618-
[c140]
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  - conf/iccd/MoTB01
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Fan Mo, Abdallah Tabbara, Robert K. Brayton: A Timing-Driven Macro-Cell Placement Algorithm. ICCD 2001: 322-327
2000
[j34]
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  - journals/fmsd/QuerCCLSB00
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Stefano Quer, Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Ellen Sentovich, Robert K. Brayton: Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks. Formal Methods in System Design 17(2): 107-134 (2000)
[j33]
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  - journals/integration/OttenB00
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Ralph H. J. M. Otten, Robert K. Brayton: Performance planning. Integration 29(1): 1-24 (2000)
[j32]
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  - journals/integration/TabbaraTBN00
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Abdallah Tabbara, Bassam Tabbara, Robert K. Brayton, A. Richard Newton: Integration of retiming with architectural floorplanning. Integration 29(1): 25-43 (2000)
[j31]
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  - journals/tcad/GoldbergCVBS00
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Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Negative thinking in branch-and-bound: the case of unate covering. IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 281-294 (2000)
[j30]
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  - journals/tcad/AzizBBS00
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Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential synthesis using S1S. IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1149-1162 (2000)
[j29]
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Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton: Model-checking continous-time Markov chains. ACM Trans. Comput. Log. 1(1): 162-170 (2000)
[c139]
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  - conf/dac/JongeneelWBO00
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Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten: Area and search space control for technology mapping. DAC 2000: 86-91
[c138]
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Fan Mo, Abdallah Tabbara, Robert K. Brayton: A Force-Directed Macro-Cell Placer. ICCAD 2000: 177-180
[c137]
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  - conf/iccad/KhatriBS00
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Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. ICCAD 2000: 412-418
[c136]
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  - conf/iccad/JiangB00
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Yunjian Jiang, Robert K. Brayton: Don't Cares and Multi-Valued Logic Network Minimization. ICCAD 2000: 520-525
[c135]
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  - conf/iccd/SinhaKBS00
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Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. ICCD 2000: 494-503

1990 – 1999

see FAQ

What is the meaning of the colors in the publication list?

1999
[c134]
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Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli: A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. DAC 1999: 491-496
[c133]
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  - conf/dac/TabbaraBN99
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Abdallah Tabbara, Robert K. Brayton, A. Richard Newton: Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints. DAC 1999: 725-730
[c132]
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Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton: Using Combinational Verification for Sequential Circuits. DATE 1999: 138-144
[c131]
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  - conf/iccad/KukimotoB99
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Yuji Kukimoto, Robert K. Brayton: Timing-safe false path removal for combinational modules. ICCAD 1999: 544-550
[c130]
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  - conf/iccad/KuehlmannMB99
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Andreas Kuehlmann, Kenneth L. McMillan, Robert K. Brayton: Probabilistic state space search. ICCAD 1999: 574-579
[c129]
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  - conf/ifip10-5/CarloniGVBS99
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Luca P. Carloni, Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems. VLSI 1999: 346-361
[c128]
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  - conf/vlsid/BraytonK99
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Robert K. Brayton, Sunil P. Khatri: Multi-Valued Logic Synthesis. VLSI Design 1999: 196-105
[c127]
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  - conf/vlsid/KhatriBS99
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Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential Multi-Valued Network Simplification using Redundancy Removal. VLSI Design 1999: 206-211
1998
[j28]
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  - journals/tcad/GoldbergVBS98
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Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Theory and algorithms for face hypercube embedding. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 472-488 (1998)
[c126]
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  - conf/ats/LiMB98
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Zhongcheng Li, Yinghua Min, Robert K. Brayton: A New Low-Cost Method for Identifying Untestable Path Delay Faults. Asian Test Symposium 1998: 76-81
[c125]
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  - conf/cav/MankuHB98
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Gurmeet Singh Manku, Ramin Hojati, Robert K. Brayton: Structural Symmetry and Model Checking. CAV 1998: 159-171
[c124]
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  - conf/cav/IslesHB98
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Adrian J. Isles, Ramin Hojati, Robert K. Brayton: Computing Reachable Control States of Systems Modeled with Uninterpreted Functions and Infinite Memory. CAV 1998: 256-267
[c123]
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  - conf/dac/OttenB98
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Ralph H. J. M. Otten, Robert K. Brayton: Planning for Performance. DAC 1998: 122-127
[c122]
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  - conf/dac/KukimotoBS98
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Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar: Delay-Optimal Technology Mapping by DAG Covering. DAC 1998: 348-351
[c121]
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  - conf/dac/KukimotoB98
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Yuji Kukimoto, Robert K. Brayton: Hierarchical Functional Timing Analysis. DAC 1998: 580-585
[c120]
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  - conf/date/GoldbergKB98
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Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton: Combinational Verification based on High-Level Functional Specifications. DATE 1998: 803-808
[c119]
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  - conf/iccad/GostiNBS98
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Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Wireplanning in logic synthesis. ICCAD 1998: 26-33
[c118]
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  dblp key:
  - conf/iccad/SinhaB98
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Subarnarekha Sinha, Robert K. Brayton: Implementation and use of SPFDs in optimizing Boolean networks. ICCAD 1998: 103-110
[c117]
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  - conf/iccad/RanjanSSB98
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Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton: On the optimization power of retiming and resynthesis transformations. ICCAD 1998: 402-407
[c116]
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  - conf/vlsid/SwamyEB98
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Gitanjali Swamy, Stephen A. Edwards, Robert K. Brayton: Efficient Verification and Synthesis using Design Commonalities. VLSI Design 1998: 542-551
1997
[j27]
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  - journals/tcad/KamVBS97
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Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Implicit computation of compatible sets for state minimization of ISFSMs. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 657-676 (1997)
[j26]
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  - journals/tcad/VillaKBS97
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Tiziano Villa, Timothy Kam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Explicit and implicit algorithms for binate covering problems. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 677-691 (1997)
[j25]
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Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Symbolic two-level minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 692-708 (1997)
[j24]
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Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Theory and algorithms for state minimization of nondeterministic FSMs. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1311-1322 (1997)
[c115]
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  - conf/cav/TasiranB97
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Serdar Tasiran, Robert K. Brayton: STARI: A Case Study in Compositional and Hierarchical Timing Verification. CAV 1997: 191-201
[c114]
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Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani: Partial-Order Reduction in Symbolic State Space Exploration. CAV 1997: 340-351
[c113]
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  - conf/dac/KukimotoB97
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Yuji Kukimoto, Robert K. Brayton: Exact Required Time Analysis via False Path Detection. DAC 1997: 220-225
[c112]
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  - conf/iccad/GoldbergCVBS97
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Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Negative thinking by incremental problem solving: application to unate covering. ICCAD 1997: 91-98
[c111]
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  - conf/iccad/KukimotoGSB97
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Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton: Approximate timing analysis of combinational circuits under the XBD0 model. ICCAD 1997: 176-181
[c110]
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  - conf/iccad/MehrotraQSBAS97
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Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli: Sequential optimisation without state space exploration. ICCAD 1997: 208-215
[c109]
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  - conf/iccad/GoldbergVBS97
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Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A fast and robust exact algorithm for face embedding. ICCAD 1997: 296-303
[c108]
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  - conf/iccad/NarayanIJBS97
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Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Reachability analysis using partitioned-ROBDDs. ICCAD 1997: 388-393
[c107]
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  - conf/iccd/RanjanGBS97
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Rajeev K. Ranjan, Wilsin Gosti, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions. ICCD 1997: 344-351
[c106]
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  - conf/iccd/LiZMB97
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Zhongcheng Li, Yuhong Zhao, Yinghua Min, Robert K. Brayton: Timed Binary Decision Diagrams. ICCD 1997: 352-357
[c105]
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  - conf/itc/LiBM97
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Zhongcheng Li, Robert K. Brayton, Yinghua Min: Efficient Identification of Non-Robustly Untestable Path Delay Faults. ITC 1997: 992-997
1996
[j23]
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  - journals/tcad/WatanabeGB96
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Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton: Permissible functions for multioutput components in combinational logic optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 732-744 (1996)
[j22]
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  - journals/tcad/LamBS96
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William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Valid clock frequencies and their computation in wavepipelined circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 791-807 (1996)
[j21]
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  - journals/tcad/StephanBS96
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Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Combinational test generation using satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1167-1176 (1996)
[c104]
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  - conf/cav/AzizSSB96
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Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton: Verifying Continuous Time Markov Chains. CAV 1996: 269-276
[c103]
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  - conf/cav/BraytonHSSACEKKPQRSSSV96
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Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS: A System for Verification and Synthesis. CAV 1996: 428-432
[c102]
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  - conf/concur/TasiranAKB96
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Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, Robert K. Brayton: Verifying Abstractions of Timed Systems. CONCUR 1996: 546-562
[c101]
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  - conf/dac/KhatriNKMBS96
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Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Engineering Change in a Non-Deterministic FSM Setting. DAC 1996: 451-456
[c100]
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  - conf/dac/SanghaviRBS96
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Jagesh V. Sanghavi, Rajeev K. Ranjan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: High Performance BDD Package By Exploiting Memory Hiercharchy. DAC 1996: 635-640
[c99]
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  dblp key:
  - conf/fmcad/HojatiIKB96
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Ramin Hojati, Adrian J. Isles, Desmond Kirkpatrick, Robert K. Brayton: Verification Using Uninterpreted Functions and Finite Instantiations. FMCAD 1996: 218-232
[c98]
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  dblp key:
  - conf/fmcad/BraytonHSSACEKKPQRSSSV96
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Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS. FMCAD 1996: 248-256
[c97]
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  - conf/fmcad/JainNCKSBF96
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Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita: Decomposition Techniques for Efficient ROBDD Construction. FMCAD 1996: 419-434
[c96]
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  dblp key:
  - conf/iccad/SinghalMB96
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Vigyan Singhal, Sharad Malik, Robert K. Brayton: The case for retiming with explicit reset circuitry. ICCAD 1996: 618-625
[c95]
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  - conf/iccd/HojatiKB96
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Ramin Hojati, Sriram C. Krishnan, Robert K. Brayton: Early Quantification and Partitioned Transition Relations. ICCD 1996: 12-19
[c94]
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  dblp key:
  - conf/iccd/RanjanSBS96
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Rajeev K. Ranjan, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Binary decision diagrams on network of workstation. ICCD 1996: 358-364
[c93]
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  dblp key:
  - conf/iccd/QadeerBS96
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Shaz Qadeer, Robert K. Brayton, Vigyan Singhal: Latch Redundancy Removal Without Global Reset. ICCD 1996: 432-439
[c92]
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  - conf/vlsid/NarayanKJFBS96
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Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design 1996: 249-253
1995
[j20]
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Ramin Hojati, Robert K. Brayton: An Environment for Formal Verification Based on Symbolic Computations. Formal Methods in System Design 6(2): 191-216 (1995)
[j19]
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  - journals/iandc/TouatiBK95
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Hervé J. Touati, Robert K. Brayton, Robert P. Kurshan: Testing Language Containment for omega-Automata Using BDD's. Inf. Comput. 118(1): 101-109 (1995)
[j18]
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Robert K. Brayton, Ellen M. Sentovich: Network Hierarchies and Node Minimization. IEICE Transactions 78-D(3): 199-208 (1995)
[j17]
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William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Delay fault coverage, test set size, and performance trade-offs. IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 32-44 (1995)
[j16]
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  - journals/tcad/LavagnoMBS95
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Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: An efficient heuristic procedure for solving the state assignment problem for event-based specifications. IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 45-60 (1995)
[c91]
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Ramin Hojati, Robert K. Brayton: Automatic Datapath Abstraction In Hardware Systems. CAV 1995: 98-113
[c90]
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  - conf/cav/KrishnanPBV95
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Sriram C. Krishnan, Anuj Puri, Robert K. Brayton, Pravin Varaiya: The Rabin Index and Chain Automata, with Applications to Automatas and Games. CAV 1995: 253-266
[c89]
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  - conf/cav/AzizBBDS95
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Adnan Aziz, Felice Balarin, Robert K. Brayton, M. D. DiBenedetto, Alexander Saldanha: Supervisory Control of Finite State Machines. CAV 1995: 279-292
[c88]
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  dblp key:
  - conf/charme/TasiranHB95
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Serdar Tasiran, Ramin Hojati, Robert K. Brayton: Language containment of non-deterministic omega-automata. CHARME 1995: 261-277
[c87]
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  dblp key:
  - conf/dac/SinghalPRB95
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Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton: The Validity of Retiming Sequential Circuits. DAC 1995: 316-321
[c86]
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  dblp key:
  - conf/eurodac/SinghalPAB95
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Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton: Exploiting power-up delay for sequential optimization. EURO-DAC 1995: 54-59
[c85]
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  dblp key:
  - conf/iccad/AzizBBS95
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Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential synthesis using S1S. ICCAD 1995: 612-617
[c84]
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  dblp key:
  - conf/iccad/WangB95
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Huey-Yih Wang, Robert K. Brayton: Multi-level logic optimization of FSM networks. ICCAD 1995: 728-735
[c83]
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  dblp key:
  - conf/iccd/KamVBS95
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Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Implicit state minimization of non-deterministic FSMs. ICCD 1995: 250-257
[c82]
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  dblp key:
  - conf/iccd/SwamyBS95
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Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal: Incremental methods for FSM traversal. ICCD 1995: 590-
[c81]
- no documents available
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  - conf/iscas/SinghalBP95
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Vigyan Singhal, Robert K. Brayton, Carl Pixley: Power-Up Delay for Retiming Digital Circuits. ISCAS 1995: 566-569
[c80]
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  - conf/stacs/KrishnanPB95
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Sriram C. Krishnan, Anuj Puri, Robert K. Brayton: Structural Complexity of Omega-Automata. STACS 1995: 143-156
[c79]
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  - conf/vlsid/SaldanhaSBS95
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Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Functional clock schedule optimization. VLSI Design 1995: 93-98
1994
[j15]
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Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Satisfaction of input and output encoding constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 589-602 (1994)
[j14]
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Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Circuit structure relations to redundancy and delay. IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 875-883 (1994)
[j13]
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  - journals/vlsisp/MoonSB94
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Cho W. Moon, Paul R. Stephan, Robert K. Brayton: Specification, synthesis, and verification of hazard-free asynchronous circuits. VLSI Signal Processing 7(1-2): 85-100 (1994)
[c78]
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  - conf/cav/LamB94
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William K. C. Lam, Robert K. Brayton: Criteria for the Simple Path Property in Timed Automata. CAV 1994: 27-40
[c77]
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  - conf/cav/HojatiMB94
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Ramin Hojati, Robert B. Mueller-Thuns, Robert K. Brayton: Improving Language Containment Using Fairness Graphs. CAV 1994: 391-403
[c76]
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  - conf/dac/LamBS94
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William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Exact Minimum Cycle Times for Finite State Machines. DAC 1994: 100-105
[c75]
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  dblp key:
  - conf/dac/ShipleHSB94
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Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton: Heuristic Minimization of BDDs Using Don't Cares. DAC 1994: 225-231
[c74]
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  dblp key:
  - conf/dac/AzizTB94
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Adnan Aziz, Serdar Tasiran, Robert K. Brayton: BDD Variable Ordering for Interacting Finite State Machines. DAC 1994: 283-288
[c73]
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  dblp key:
  - conf/dac/MurgaiBS94
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Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Optimum Functional Decomposition Using Encoding. DAC 1994: 408-414
[c72]
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  dblp key:
  - conf/dac/SaldanhaHMBS94
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Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Performance Optimization Using Exact Sensitization. DAC 1994: 425-429
[c71]
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  dblp key:
  - conf/dac/AzizBCHKKRSSTWBS94
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Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459
[c70]
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  dblp key:
  - conf/dac/WangB94
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Huey-Yih Wang, Robert K. Brayton: Permissible Observability Relations in FSM Networks. DAC 1994: 677-683
[c69]
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  dblp key:
  - conf/dac/KamVBS94
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Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A Fully Implicit Algorithm for Exact State Minimization. DAC 1994: 684-690
[c68]
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  - conf/eurodac/WatanabeB94
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Yosinori Watanabe, Robert K. Brayton: State Minimization of Pseudo Non-Deterministic FSM's. EDAC-ETC-EUROASIC 1994: 184-191
[c67]
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  - conf/icalp/AzizSBBS94
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Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Equivalences for Fair Kripke Structures. ICALP 1994: 364-375
[c66]
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  dblp key:
  - conf/iccad/PixleySAB94
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Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton: Multi-level synthesis for safe replaceability. ICCAD 1994: 442-449
[c65]
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  dblp key:
  - conf/iccad/SwamyB94
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Gitanjali Swamy, Robert K. Brayton: Incremental formal design verification. ICCAD 1994: 458-465
[c64]
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  dblp key:
  - conf/iccad/KukimotoFB94
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Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton: A redesign technique for combinational circuits based on gate reconnections. ICCAD 1994: 632-637
[c63]
- no documents available
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  dblp key:
  - conf/iccd/SentovichB94
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Ellen Sentovich, Robert K. Brayton: An Exact Optimization of Two-Level Acyclic Sequential Circuits. ICCD 1994: 242-249
[c62]
- no documents available
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  dblp key:
  - conf/iccd/AzizSSB94
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Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton: Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. ICCD 1994: 255-261
[c61]
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  - conf/isaac/KrishnanPB94
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Sriram C. Krishnan, Anuj Puri, Robert K. Brayton: Deterministic w Automata vis-a-vis Deterministic Buchi Automata. ISAAC 1994: 378-386
1993
[j12]
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  - journals/tc/MalikBNS93
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Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: Two-Level Minimization of Multivalued Functions with Large Offsets. IEEE Trans. Computers 42(11): 1325-1342 (1993)
[j11]
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  dblp key:
  - journals/tcad/TouatiB93
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Hervé J. Touati, Robert K. Brayton: Computing the initial states of retimed circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 157-162 (1993)
[j10]
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  - journals/tcad/MalikSBS93
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Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 568-578 (1993)
[j9]
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  - journals/tcad/WatanabeB93
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Yosinori Watanabe, Robert K. Brayton: Heuristic minimization of multiple-valued relations. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1458-1472 (1993)
[j8]
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  - journals/tvlsi/McGeerSBS93
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Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: ESPRESSO-SIGNATURE: a new exact minimizer for logic functions. IEEE Trans. VLSI Syst. 1(4): 432-440 (1993)
[c60]
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  - conf/cav/Brayton93
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Robert K. Brayton: Logic Synthesis and Design Verification. CAV 1993: 1-2
[c59]
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  dblp key:
  - conf/cav/HojatiBK93
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Ramin Hojati, Robert K. Brayton, Robert P. Kurshan: BDD-Based Debugging Of Design Using Language Containment and Fair CTL. CAV 1993: 41-58
[c58]
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  - conf/cav/LamB93
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William K. C. Lam, Robert K. Brayton: Alternating RQ Timed Automata. CAV 1993: 237-252
[c57]
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  dblp key:
  - conf/dac/MoonB93
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Cho W. Moon, Robert K. Brayton: Elimination of Dynamic hazards by Factoring. DAC 1993: 7-13
[c56]
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  dblp key:
  - conf/dac/LamBS93
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William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions. DAC 1993: 128-134
[c55]
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  dblp key:
  - conf/dac/MurgaiBS93
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Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential Synthesis for Table Look Up Programmable Gate Arrays. DAC 1993: 224-229
[c54]
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  dblp key:
  - conf/dac/MatsunagaMB93
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Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton: On Computing the Transitive Closure of a State Transition Relation. DAC 1993: 260-265
[c53]
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  dblp key:
  - conf/dac/LamSBS93
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William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Delay Fault Coverage and Performance Tradeoffs. DAC 1993: 446-452
[c52]
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  - conf/dac/HojatiSBK93
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Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan: A Unified Approach to Language Containment and Fair CTL Model Checking. DAC 1993: 475-481
[c51]
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  dblp key:
  - conf/dac/ShenoyBS93
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Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Resynthesis of Multi-Phase Pipelines. DAC 1993: 490-496
[c50]
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  dblp key:
  - conf/dac/McGeerSBS93
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Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Espresso-Signature: A New Exact Minimizer for Logic Functions. DAC 1993: 618-624
[c49]
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  - conf/iccad/MurgaiBS93
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Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Cube-packing and two-level minimization. ICCAD 1993: 115-122
[c48]
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  dblp key:
  - conf/iccad/ShenoyBS93
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Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Minimum padding to satisfy short path constraints. ICCAD 1993: 156-161
[c47]
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  dblp key:
  - conf/iccad/WatanabeB93
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Yosinori Watanabe, Robert K. Brayton: The maximum set of permissible behaviors for FSM networks. ICCAD 1993: 316-320
[c46]
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  dblp key:
  - conf/iccad/WangB93
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Huey-Yih Wang, Robert K. Brayton: Input don't care sequences in FSM networks. ICCAD 1993: 321-328
[c45]
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  dblp key:
  - conf/iccd/WatanabeGB93
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Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton: Logic Optimization with Multi-Output Gates. ICCD 1993: 416-420
[c44]
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  dblp key:
  - conf/iccd/SinghalWB93
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Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton: Heuristic Minimization of Synchronous Relations. ICCD 1993: 428-433
[c43]
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  dblp key:
  - conf/iccd/StephanB93
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Paul R. Stephan, Robert K. Brayton: Physically Realizable Gate Models. ICCD 1993: 442-445
[c42]
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  dblp key:
  - conf/iccd/MurgaiBS93
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Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. ICCD 1993: 505-512
[c41]
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  - conf/vlsid/McGeerSBS93
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Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Minimization of Logic Functions Using Essential Signature Sets. VLSI Design 1993: 323-328
1992
[j7]
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  - journals/tcad/MalikLBS92
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Sharad Malik, Luciano Lavagno, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Symbolic minimization of multilevel logic and the input encoding problem. IEEE Trans. on CAD of Integrated Circuits and Systems 11(7): 825-843 (1992)
[c40]
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  - conf/cav/ShipleCSB92
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Thomas R. Shiple, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton: Automatic Reduction in CTL Compositional Model Checking. CAV 1992: 234-247
[c39]
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Ramin Hojati, Hervé J. Touati, Robert P. Kurshan, Robert K. Brayton: Efficient omega-Regular Language Containment. CAV 1992: 396-409
[c38]
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Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. DAC 1992: 173-176
[c37]
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  - conf/dac/SaldanhaBS92a
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Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. DAC 1992: 245-248
[c36]
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  - conf/dac/MurgaiBS92
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Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: An Improved Synthesis Algorithm for Multiplexor-Based PGA's. DAC 1992: 380-386
[c35]
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  - conf/dac/ShenoySBS92
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Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: On the Temporal Equivalence of Sequential Circuits. DAC 1992: 405-409
[c34]
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Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Solving the State Assignment Problem for Signal Transition Graphs. DAC 1992: 568-572
[c33]
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Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Graph algorithms for clock schedule optimization. ICCAD 1992: 132-136
[c32]
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  - conf/iccad/ChiodoSSB92
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Massimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton: Automatic compositional minimization in CTL model checking. ICCAD 1992: 172-178
[c31]
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  - conf/iccad/LamBS92
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William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Valid clocking in wavepipelined circuits. ICCAD 1992: 518-525
[c30]
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  - conf/iccd/SentovichSMSBS92
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Ellen Sentovich, Kanwar Jit Singh, Cho W. Moon, Hamid Savoj, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential Circuit Design Using Synthesis and Optimization. ICCD 1992: 328-333
[c29]
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William K. C. Lam, Robert K. Brayton: On Relationship Between ITE and BDD. ICCD 1992: 448-451
[c28]
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  - conf/iccd/GutwinMB92
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Paul T. Gutwin, Patrick C. McGeer, Robert K. Brayton: Delay Prediction for Technology-Independent Logic Equations. ICCD 1992: 468-471
1991
[j6]
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  - journals/tcad/MalikSBS91
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Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Retiming and resynthesis: optimizing sequential networks with combinational techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 74-84 (1991)
[j5]
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  - journals/tcad/MalikBNS91
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Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: Reduced offsets for minimization of binary-valued functions. IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 413-426 (1991)
[c27]
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  - conf/dac/SaldanhaVBS91
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Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A Framework for Satisfying Input and Output Encoding Constraints. DAC 1991: 170-175
[c26]
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  - conf/iccad/MurgaiBS91
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Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: On Clustering for Minimum Delay/Area. ICCAD 1991: 6-9
[c25]
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  - conf/iccad/WatanbeB91
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Yosinori Watanabe, Robert K. Brayton: Heuristic Minimazation of Multiple-Valued Relations. ICCAD 1991: 126-129
[c24]
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  - conf/iccad/McGeerSSBS91
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Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. ICCAD 1991: 180-183
[c23]
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Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Sartaj Sahni: Performance Enhancement through the Generalized Bypass Transform. ICCAD 1991: 184-187
[c22]
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  - conf/iccad/TouatiSB91
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Hervé J. Touati, Hamid Savoj, Robert K. Brayton: Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing. ICCAD 1991: 188-191
[c21]
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  - conf/iccad/MoonSB91
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Cho W. Moon, Paul R. Stephan, Robert K. Brayton: Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. ICCAD 1991: 322-325
[c20]
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  - conf/iccad/SavojBT91
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Hamid Savoj, Robert K. Brayton, Hervé J. Touati: Extracting Local Don't Cares for Network Optimization. ICCAD 1991: 514-517
[c19]
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Hamid Savoj, Robert K. Brayton: Observability Relations and Observability Don't Cares. ICCAD 1991: 518-521
[c18]
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Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Improved Logic Synthesis Algorithms for Table Look Up Architectures. ICCAD 1991: 564-567
[c17]
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  - conf/iccad/MurgaiSBS91a
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Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. ICCAD 1991: 572-575
[c16]
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  - conf/iccd/WatanabeB91
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Yosinori Watanabe, Robert K. Brayton: Incremental Synthesis for Engineering Changes. ICCD 1991: 40-43
[c15]
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Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Retiming of Circuits with Single Phase Transparent Latches. ICCD 1991: 86-89
[c14]
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Abdul A. Malik, David Harrison, Robert K. Brayton: Three-Level Decomposition with Application to PLDs. ICCD 1991: 628-633
[c13]
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Ellen Sentovich, Robert K. Brayton: Preserving Don't Care Conditions During Retiming. VLSI 1991: 461-470
1990
[c12]
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  - conf/dac/McGeerB90
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Patrick C. McGeer, Robert K. Brayton: Timing Analysis in Precharge/Unate Networks. DAC 1990: 124-129
[c11]
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  - conf/dac/MalikBNS90
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Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: Reduced Offsets for Two-Level Multi-Valued Logic Minimization. DAC 1990: 290-296
[c10]
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  - conf/dac/SavojB90
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Hamid Savoj, Robert K. Brayton: The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks. DAC 1990: 297-301
[c9]
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Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Logic Synthesis for Programmable Gate Arrays. DAC 1990: 620-625
[c8]
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  - conf/iccad/SrinivasanKMB90
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Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton: Algorithms for Discrete Function Manipulation. ICCAD 1990: 92-95
[c7]
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  - conf/iccad/TouatiSLBS90
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Hervé J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Implicit State Enumeration of Finite State Machines Using BDDs. ICCAD 1990: 130-133
[c6]
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Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Performance Optimization of Pipelined Circuits. ICCAD 1990: 410-413
[c5]
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Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng: Timing Optimization with Testability Considerations. ICCAD 1990: 460-463
[c4]
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  - conf/iccad/LavagnoMBS90
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Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. ICCAD 1990: 560-563

1980 – 1989

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What is the meaning of the colors in the publication list?

1989
[c3]
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Patrick C. McGeer, Robert K. Brayton: Efficient Prime Factorization of Logic Expressions. DAC 1989: 221-225
[c2]
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Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Multi-level Logic Simplification Using Don't Cares and Filters. DAC 1989: 277-282
[c1]
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Patrick C. McGeer, Robert K. Brayton: Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network. DAC 1989: 561-567
1988
[j4]
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  - journals/tcad/BartlettBHJMRSW88
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Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang: Multi-level logic minimization using implicit don't cares. IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 723-740 (1988)
1987
[j3]
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  - journals/tcad/BraytonRSW87
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Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang: MIS: A Multiple-Level Logic Optimization System. IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 1062-1081 (1987)
1986
[j2]
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  - journals/tcad/MicheliBS86
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Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Correction to "Optimal State Assignment for Finite State Machines". IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 239 (1986)
1985
[j1]
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Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Optimal State Assignment for Finite State Machines. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 269-285 (1985)

Coauthor Index

see FAQ

What is the meaning of the colors in the coauthor index?