Melvin A. Breuer

Yue Gao, Sandeep K. Gupta, Melvin A. Breuer: Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors. DATE 2013: 927-932

Yue Gao, Melvin A. Breuer, Yanzhi Wang: A new paradigm for trading off yield, area and performance to enhance performance per wafer. DATE 2013: 1753-1758

Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer: Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. IEEE Trans. on CAD of Integrated Circuits and Systems 31(5): 754-764 (2012)

Zhaoliang Pan, Melvin A. Breuer: Error Rate Estimation for Defective Circuits via Ones Counting. ACM Trans. Design Autom. Electr. Syst. 17(1): 8 (2012)

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian: Theory of redundancy for logic circuits to maximize yield/area. ISQED 2012: 663-671

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta: A design flow to maximize yield/area of physical devices via redundancy. ITC 2012: 1-10

Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. IEEE Trans. on CAD of Integrated Circuits and Systems 30(6): 930-934 (2011)

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta: HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC. Asian Test Symposium 2010: 249-254

Melvin A. Breuer: Hardware that produces bounded rather than exact results. DAC 2010: 871-876

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta: Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. DATE 2010: 1249-1254

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta: SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. Asian Test Symposium 2009: 193-199

Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee: Tolerance of performance degrading faults for effective yield improvement. ITC 2009: 1-10

Melvin A. Breuer, Haiyang (Henry) Zhu: An Illustrated Methodology for Analysis of Error Tolerance. IEEE Design & Test of Computers 25(2): 168-177 (2008)

Melvin A. Breuer: Clarifying the record on testability cost functions. IEEE Design & Test of Computers 25(6): 608-609 (2008)

Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: An Error Rate Based Test Methodology to Support Error-Tolerance. IEEE Transactions on Reliability 57(1): 204-214 (2008)

Zhaoliang Pan, Melvin A. Breuer: Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER). VTS 2008: 59-66

Zhaoliang Pan, Melvin A. Breuer: Estimating Error Rate in Defective Logic Using Signature Analysis. IEEE Trans. Computers 56(5): 650-661 (2007)

Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: Reduction of detected acceptable faults for yield improvement via error-tolerance. DATE 2007: 1599-1604

Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer: STAX: statistical crosstalk target set compaction. DATE Designers' Forum 2006: 172-177

Melvin A. Breuer, Haiyang (Henry) Zhu: Error-Tolerance and Multi-Media. IIH-MSP 2006: 521-524

Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. VTS 2006: 130-135

Melvin A. Breuer: Multi-media Applications and Imprecise Computation. DSD 2005: 2-7

Melvin A. Breuer: Let's Think Analog. ISVLSI 2005: 2-5

Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer: Multiple tests for each gate delay fault: higher coverage and lower test application cost. ITC 2005: 9

Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer: A novel test methodology based on error-rate to support error-tolerance. ITC 2005: 9

Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak: Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Design & Test of Computers 21(3): 216-227 (2004)

Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian: Efficient Identification of Crosstalk Induced Slowdown Targets. Asian Test Symposium 2004: 124-131

Melvin A. Breuer: Intelligible Test Techniques to Support Error-Tolerance. Asian Test Symposium 2004: 386-393

Lei Wang, Sandeep K. Gupta, Melvin A. Breuer: Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. Asian Test Symposium 2004: 440-447

Melvin A. Breuer: Determining error rate in error tolerant VLSI chips. DELTA 2004: 321-326

Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer: Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. ITC 2004: 1024-1033

Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer: An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. Asian Test Symposium 2003: 174-177

Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Maximizing Ground Bounce Considering Circuit Delay. VTS 2003: 151-157

Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer: Analyzing Crosstalk in the Presence of Weak Bridge Defects. VTS 2003: 385-392

Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. J. Electronic Testing 18(1): 17-28 (2002)

Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: TA-PSV - Timing Analysis for Partially Specified Vectors. J. Electronic Testing 18(1): 73-88 (2002)

Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Analytical models for crosstalk excitation and propagation in VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1117-1131 (2002)

I-De Huang, Sandeep K. Gupta, Melvin A. Breuer: Accurate and Efficient Static Timing Analysis with Crosstalk. ICCD 2002: 265-272

Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: XIDEN: Crosstalk Target Identification Framework. ITC 2002: 365-374

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Introducing redundant computations in RTL data paths for reducing BIST resources. ACM Trans. Design Autom. Electr. Syst. 6(3): 423-445 (2001)

Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: A New Gate Delay Model for Simultaneous Switching and Its Applications. DAC 2001: 289-294

Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: Switch-level delay test of domino logic circuits. ITC 2001: 367-376

Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer: Crosstalk test generation on pseudo industrial circuits: a case study. ITC 2001: 548-557

Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. VTS 2001: 358-367

Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Novel Test Pattern Generators for Pseudoexhaustive Testing. IEEE Trans. Computers 49(11): 1228-1240 (2000)

Melvin A. Breuer, Majid Sarrafzadeh, Fabio Somenzi: Fundamental CAD algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 19(12): 1449-1475 (2000)

Melvin A. Breuer, Kwang-Ting Cheng: Challenges for the Academic Test Community. Asian Test Symposium 2000: 4-

Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: A new framework for static timing analysis, incremental timing refinement, and timing simulation. Asian Test Symposium 2000: 102-107

Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation for crosstalk-induced faults: framework and computational result. Asian Test Symposium 2000: 305-310

Melvin A. Breuer, Sandeep K. Gupta: New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. VLSI Design 2000: 8

Melvin A. Breuer: High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability. VTS 2000: 473-474

Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer: Validation and test generation for oscillatory noise in VLSI interconnects. ICCAD 1999: 289-296

Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: Switch-level delay test. ITC 1999: 171-180

Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation for crosstalk-induced delay in integrated circuits. ITC 1999: 191-200

Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Ground Bounce in Internal Logic Circuitry. VTS 1999: 95-105

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Allocation Techniques for Reducing BIST Area Overhead of Data Paths. J. Electronic Testing 13(2): 149-166 (1998)

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Estimation of BIST Resources During High-Level Synthesis. J. Electronic Testing 13(3): 221-237 (1998)

Debaditya Mukherjee, Melvin A. Breuer: An IEEE 1149.1 Compliant Test Control Architecture. J. Electronic Testing 13(3): 273-297 (1998)

Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Bounds on pseudoexhaustive test lengths. IEEE Trans. VLSI Syst. 6(3): 420-431 (1998)

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Introducing Redundant Computations in a Behavior for Reducing BIST Resources. DAC 1998: 548-553

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Scheduling and Module Assignment for Reducing Bist Resources. DATE 1998: 66-73

Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta: Process Variations and their Impact on Circuit Operation. DFT 1998: 73-

Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation in VLSI circuits for crosstalk noise. ITC 1998: 641-650

Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta: Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. ITC 1997: 809-818

Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: High Quality Robust Tests for Path Delay Faults. VTS 1997: 88-93

Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Analysis of Ground Bounce in Deep Sub-Micron Circuits. VTS 1997: 110-116

Melvin A. Breuer, Bozena Kaminska, J. McDermid, V. Rayapathi, Donald L. Wheater: Will 0.1um Digital Circuits Require Mixed-Signal Testing. VTS 1997: 186-187

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Lower Bounds on Test Resources for Scheduled Data Flow Graphs. DAC 1996: 143-148

Melvin A. Breuer, Sandeep K. Gupta: Process-Aggravated Noise (PAN): New Validation and Test Problems. ITC 1996: 914-923

Rajesh Gupta, Melvin A. Breuer: Partial scan design of register-transfer level circuits. J. Electronic Testing 7(1-2): 25-46 (1995)

Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer: Test embedding with discrete logarithms. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 554-566 (1995)

Sridhar Narayanan, Melvin A. Breuer: Reconfiguration techniques for a single scan chain. IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 750-765 (1995)

Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer: An integrated system for assigning signal flow directions to CMOS transistors. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1445-1458 (1995)

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. DAC 1995: 395-401

Sridhar Narayanan, Melvin A. Breuer: Asynchronous multiple scan chain. VTS 1995: 270-276

Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer: SWiTEST: a switch level test generation system for CMOS combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 625-637 (1994)

Ishwar Parulkar, Melvin A. Breuer, Charles Njinda: Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. DAC 1994: 345-356

Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer: A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. EDAC-ETC-EUROASIC 1994: 106-112

Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer: Control Strategies for Chip-Based DFT/BIST Hardware. ITC 1994: 893-902

Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer: Test embedding with discrete logarithms. VTS 1994: 74-80

Sen-Pin Lin, Charles Njinda, Melvin A. Breuer: Generating a family of testable designs using the BILBO methodology. J. Electronic Testing 4(1): 71-89 (1993)

Jung-Cheun Lien, Melvin A. Breuer: Test program synthesis for modules and chips having boundary scan. J. Electronic Testing 4(2): 159-180 (1993)

Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer: Optimal Configuring of Multiple Scan Chains. IEEE Trans. Computers 42(9): 1121-1131 (1993)

Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. DAC 1993: 242-248

Sridhar Narayanan, Melvin A. Breuer: Reconfigurable scan chains: a novel approach to reduce test application time. ICCAD 1993: 710-715

Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer: Merging multiple FSM controllers for DFT/BIST hardware. ICCAD 1993: 720-725

Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Novel Test Pattern Generators for Pseudo-Exhaustive Testing. ITC 1993: 1041-1050

Kuen-Jong Lee, Melvin A. Breuer: Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 659-670 (1992)

Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer: SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. DAC 1992: 26-29

Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer: Configuring multiple scan chains for minimum test time. ICCAD 1992: 4-8

Sridhar Narayanan, Charles Njinda, Melvin A. Breuer: Optimal Sequencing of Scan Registers. ITC 1992: 293-302

Rajiv Gupta, Rajagopalan Srinivasan, Melvin A. Breuer: Reorganizing Circuits to Aid Testability. IEEE Design & Test of Computers 8(3): 49-57 (1991)

Asad A. Ismaeel, Melvin A. Breuer: The probability of error detection in sequential circuits using random test vectors. J. Electronic Testing 1(4): 245-256 (1991)

Jung-Cheun Lien, Melvin A. Breuer: An optimal scheduling algorithm for testing interconnect using boundary scan. J. Electronic Testing 2(1): 117-130 (1991)

Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer: Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. ICCAD 1991: 236-239

Rajesh Gupta, Melvin A. Breuer: Ordering Storage Elements in a Single Scan Chain. ICCAD 1991: 408-411

Sen-Pin Lin, Charles Njinda, Melvin A. Breuer: A Systematic Approach for Designing Testable VLSI Circuits. ICCAD 1991: 496-499

Jung-Cheun Lien, Melvin A. Breuer: Maximal Diagnosis for Wiring Networks. ITC 1991: 96-105

Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman: Digital systems testing and testable design. Computer Science Press 1990, isbn 978-0-7167-8179-0, pp. I-XXI, 1-653

A. Majumdar, C. S. Raghavendra, Melvin A. Breuer: Fault Tolerance in Linear Systolic Arrays Using Time Redundancy. IEEE Trans. Computers 39(2): 269-276 (1990)

Rajesh Gupta, Rajiv Gupta, Melvin A. Breuer: The BALLAST Methodology for Structured Partial Scan Design. IEEE Trans. Computers 39(4): 538-544 (1990)

Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer: A New Method for Assigning Signal Flow Directions to MOS Transistors. ICCAD 1990: 492-495

Rajiv Gupta, Melvin A. Breuer: An Extensible User Interface for an Object-Oriented VLSI CAD Framework. ICSI 1990: 559-568

Melvin A. Breuer: Obstacles and an approach towards concurrent engineering. ITC 1990: 260-261

Kuen-Jong Lee, Melvin A. Breuer: On the charge sharing problem in CMOS stuck-open fault testing. ITC 1990: 417-426

Rajiv Gupta, Wesley H. Cheng, Rajesh Gupta, Ido Hardonag, Melvin A. Breuer: An Object-Oriented VLSI CAD Framework: A Case Study in Rapid Prototyping. IEEE Computer 22(5): 28-37 (1989)

Mandalagiri S. Chandrasekhar, Melvin A. Breuer: Optimal routing of two rectangular blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 8(4): 413-430 (1989)

Rajesh Gupta, Melvin A. Breuer: BALLAST: a methodology for partial scan design. FTCS 1989: 118-125

Salim U. Chowdhury, Melvin A. Breuer: Optimum design of IC power/ground nets subject to reliability constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 7(7): 787-796 (1988)

Sarma Sastry, Melvin A. Breuer: Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. IEEE Trans. on CAD of Integrated Circuits and Systems 7(9): 933-946 (1988)

Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien: Concurrent Control of Multiple BIT Structures. ITC 1988: 431-442

Melvin A. Breuer, Jung-Cheun Lien: A Test and Maintenance Controller for a Module Containing Testable Chips. ITC 1988: 502-513

Magdy S. Abadir, Melvin A. Breuer: Test Schedules for VLSI Circuits Having Built-In Test Hardware. IEEE Trans. Computers 35(4): 361-367 (1986)

Melvin A. Breuer, Asad A. Ismaeel: Roving Emulation as a Fault Detection Mechanism. IEEE Trans. Computers 35(11): 933-939 (1986)

Xi-an Zhu, Melvin A. Breuer: A Knowledge-Based TDM Selection System. FJCC 1986: 854-863

Magdy S. Abadir, Melvin A. Breuer: Scan Path with Look Ahead Shifting (SPLASH). ITC 1986: 696-704

Ting-Hua Chen, Melvin A. Breuer: Automatic Design for Testability Via Testability Measures. IEEE Trans. on CAD of Integrated Circuits and Systems 4(1): 3-11 (1985)

Melvin A. Breuer, Xi-an Zhu: A knowledge based system for selecting a test methodology for a PLA. DAC 1985: 259-265

Salim U. Chowdhury, Melvin A. Breuer: The construction of minimal area power and ground nets for VLSI circuits. DAC 1985: 794-797

Israel Koren, Melvin A. Breuer: On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays. IEEE Trans. Computers 33(1): 21-27 (1984)

Harold W. Carter, Melvin A. Breuer: Efficient Single-Layer Routing Along a Line of Points. IEEE Trans. on CAD of Integrated Circuits and Systems 2(4): 259-266 (1983)

Alexander Iosupovicz, Clarence King, Melvin A. Breuer: A module interchange placement machine. DAC 1983: 171-174

Dah-Juh Chyan, Melvin A. Breuer: A placement algorithm for array processors. DAC 1983: 182-188

Miron Abramovici, Melvin A. Breuer: Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis. IEEE Trans. Computers 31(12): 1165-1172 (1982)

Melvin A. Breuer: A survey of the state-of-the-art of design automation an invited presentation. DAC 1982: 1

Mandalagiri S. Chandrasekhar, Melvin A. Breuer: Optimum placement of two rectangular blocks. DAC 1982: 879-886

Zahir A. Syed, Abbas El Gamal, Melvin A. Breuer: On routing for custom integrated circuits. DAC 1982: 887-893

Sarangan Krishna Kumar, Melvin A. Breuer: Probabilistic Aspects of Boolean Switching Functions via a New Transform. J. ACM 28(3): 502-520 (1981)

Melvin A. Breuer, Alice C. Parker: Digital system simulation: Current status and future trends or darwin's theory of simulation. DAC 1981: 269-275

Prathima Agrawal, Melvin A. Breuer: A probabilistic model for the analysis of the routing process for circuits. Networks 10(2): 111-127 (1980)

Melvin A. Breuer, Arthur D. Friedman: Functional Level Primitives in Test Generation. IEEE Trans. Computers 29(3): 223-235 (1980)

Miron Abramovici, Melvin A. Breuer: Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis. IEEE Trans. Computers 29(6): 451-460 (1980)

Miron Abramovici, Melvin A. Breuer: Fault diagnosis based on effect-cause analysis: An introduction. DAC 1980: 69-76

Prathima Agrawal, Melvin A. Breuer: Experiments with a Density Router for PC Cards. IEEE Trans. Computers 28(3): 262-267 (1979)

Miron Abramovici, Melvin A. Breuer: On Redundancy and Fault Detection in Sequential Circuits. IEEE Trans. Computers 28(11): 864-865 (1979)

Harold W. Carter, Melvin A. Breuer, Zahir A. Syed: Incremental processing applied to Steinberg's placement procedure. DAC 1979: 26-31

Danny C. C. Ko, Melvin A. Breuer: The design of self-checking multi-output combinational circuits. AFIPS National Computer Conference 1977: 711-721

Prathima Agarwal, Melvin A. Breuer: Some theoretical aspects of algorithmic routing. DAC 1977: 23-31

Miron Abramovici, Melvin A. Breuer, K. Kumar: Concurrent fault simulation and functional level modeling. DAC 1977: 128-137

Melvin A. Breuer: A class of min-cut placement algorithms. DAC 1977: 284-290

Melvin A. Breuer, Shih-Jeh Chang, Stephen Y. H. Su: Identification of Multiple Stuck-Type Faults in Combinational Networks. IEEE Trans. Computers 25(1): 44-54 (1976)

Melvin A. Breuer, Arthur D. Friedman: Initial design concepts for an advanced design automation system. DAC 1974: 366-371

Melvin A. Breuer: Simplification of the Covering Problem with Application to Boolean Expressions. J. ACM 17(1): 166-181 (1970)

Melvin A. Breuer: Generation of optimal code for expressions via factorization. Commun. ACM 12(6): 333-340 (1969)

Melvin A. Breuer: Combinatorial Equivalence of (0, 1) Circulant Matrices. J. Comput. Syst. Sci. 3(1): 8-23 (1969)

Melvin A. Breuer: Fault Detection in a Linear Cascade of Identical Machines. SWAT (FOCS) 1968: 235-243

Melvin A. Breuer: Adaptive Computers. Information and Control 11(4): 402-422 (1967)

Melvin A. Breuer: The application of integer programming in design automation. DAC 1966

Melvin A. Breuer: Techniques for the simulation of computer logic. Commun. ACM 7(7): 443-446 (1964)