Javier D. Bruguera

E. G. Paredes, Montserrat Bóo, Margarita Amor, Javier D. Bruguera, Jürgen Döllner: Extended hybrid meshing algorithm for multiresolution terrain models. International Journal of Geographical Information Science 26(5): 771-793 (2012)

Marc Daumas, Javier D. Bruguera: 8th Conference on Real Numbers and Computers. Inf. Comput. 216: 1-2 (2012)

Lois Orosa, Elisardo Antelo, Javier D. Bruguera: FlexSig: Implementing flexible hardware signatures. TACO 8(4): 30 (2012)

E. G. Paredes, Montserrat Bóo, Margarita Amor, Jürgen Döllner, Javier D. Bruguera: GPU-based Visualization of Hybrid Terrain Models. GRAPP/IVAPP 2012: 254-259

Javier D. Bruguera, Marius Cornea, Debjit Das Sarma: Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 60(2): 145-147 (2011)

Daniel Piso Fernandez, Javier D. Bruguera: Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate. IEEE Trans. Computers 60(11): 1535-1546 (2011)

Alvaro V'zquez, Javier D. Bruguera: Composite Iterative Algorithm and Architecture for q-th Root Calculation. IEEE Symposium on Computer Arithmetic 2011: 52-61

Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera: High Performance Image Processing on a Massively Parallel Processor Array. DSD 2009: 233-236

Daniel Piso Fernandez, Javier D. Bruguera: Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation. DSD 2009: 293-300

Javier D. Bruguera, Marius Cornea, Debjit Das Sarma, John Harrison (Eds.): 19th IEEE Symposium on Computer Arithmetic, ARITH 2009, Portland, Oregon, USA, 9-10 June 2009. IEEE Computer Society 2009, isbn 978-0-7695-3670-5

Alex Piñeiro, Javier D. Bruguera, Fabrizio Lamberti, Paolo Montuschi: A Radix-2 Digit-by-Digit Architecture for Cube Root. IEEE Trans. Computers 57(4): 562-566 (2008)

Roberto R. Osorio, Javier D. Bruguera: An FPGA architecture for CABAC decoding in manycore systems. ASAP 2008: 293-298

Daniel Piso Fernandez, Javier D. Bruguera: A New Rounding Algorithm for Variable Latency Division and Square Root Implementations. DSD 2008: 760-767

Hans-Joachim Bungartz, Javier D. Bruguera, Peter Arbenz, Bruce Hendrickson: Topic 10: Parallel Numerical Algorithms. Euro-Par 2008: 778-779

F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Hardware support for adaptive tessellation of Bézier surfaces based on local tests. Journal of Systems Architecture 53(4): 233-250 (2007)

Paolo Montuschi, Javier D. Bruguera, Luigi Ciminiera, José-Alejandro Piñeiro: A Digit-by-Digit Algorithm for mth Root Extraction. IEEE Trans. Computers 56(12): 1696-1706 (2007)

Roberto R. Osorio, Javier D. Bruguera: Entropy Coding on a Programmable Processor Array for Multimedia SoC. ASAP 2007: 222-227

Roberto R. Osorio, Javier D. Bruguera: High-Throughput Architecture for H.264/AVC CABAC Compression System. IEEE Trans. Circuits Syst. Video Techn. 16(11): 1376-1384 (2006)

Viay Holimath, Javier D. Bruguera: A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table. DSD 2006: 236-239

Roberto R. Osorio, Javier D. Bruguera: A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. DSD 2006: 269-274

Javier D. Bruguera, Roberto R. Osorio: A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. DSD 2006: 407-414

José-Alejandro Piñeiro, Stuart F. Oberman, Jean-Michel Muller, Javier D. Bruguera: High-Speed Function Approximation Using a Minimax Quadratic Interpolator. IEEE Trans. Computers 54(3): 304-318 (2005)

José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. VLSI Signal Processing 40(1): 109-123 (2005)

Javier D. Bruguera, Tomás Lang: Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition. IEEE Symposium on Computer Arithmetic 2005: 42-51

Roberto R. Osorio, Javier D. Bruguera: A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. DSD 2005: 298-305

F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Adaptive Tessellation of Bezier Surfaces Based on Displacement Maps. WSCG (Short Papers) 2005: 29-32

Tomás Lang, Javier D. Bruguera: Floating-Point Multiply-Add-Fused with Reduced Latency. IEEE Trans. Computers 53(8): 988-1003 (2004)

José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. IEEE Trans. Computers 53(9): 1085-1096 (2004)

Roberto R. Osorio, Javier D. Bruguera: Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. DSD 2004: 62-69

Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Algorithms and Hardware for Data Compression in Point Rendering Applications. WSCG (Short Papers) 2004: 173-180

Juan Touriño, Jorge Parapar, Ramon Doallo, Marcos Boullón, Francisco F. Rivera, Javier D. Bruguera, Xesús P. González, Rafael Crecente, Carlos Álvarez: Research Article: A GIS-embedded system to support land consolidation plans in Galicia. International Journal of Geographical Information Science 17(4): 377-396 (2003)

Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera: Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor. Journal of Systems Architecture 49(12-15): 543-555 (2003)

María J. Martín, David E. Singh, José Carlos Mouriño, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera: High performance air pollution modeling for a power plant environment. Parallel Computing 29(11-12): 1763-1790 (2003)

Javier D. Bruguera, Tomás Lang: Multilevel Reverse-Carry Addition: Single and Dual Adders. VLSI Signal Processing 33(1-2): 55-74 (2003)

José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: High-Radix Iterative Algorithm for Powering Computation. IEEE Symposium on Computer Arithmetic 2003: 204-211

José-Alejandro Piñeiro, Javier D. Bruguera, Milos D. Ercegovac: On-line high-radix exponential with selection by rounding. ISCAS (4) 2003: 121-124

F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Adaptive Tessellation of NURBS Surfaces. WSCG 2003

José-Alejandro Piñeiro, Javier D. Bruguera: High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root. IEEE Trans. Computers 51(12): 1377-1388 (2002)

Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes. 3DPVT 2002: 380-383

José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: High-Radix Logarithm with Selection by Rounding. ASAP 2002: 101-110

Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera: Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. DSD 2002: 218-225

Ángel del Río, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Hardware Implementation of the Subdivision Loop Algorithm. EUROMICRO 2002: 189-199

José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. ICCD 2002: 132-137

Tomás Lang, Javier D. Bruguera: Floating-Point Fused Multiply-Add with Reduced Latency. ICCD 2002: 145-

Javier D. Bruguera, Tomás Lang: Multilevel reverse most-significant carry computation. IEEE Trans. VLSI Syst. 9(6): 959-962 (2001)

José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller: Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree. IEEE Symposium on Computer Arithmetic 2001: 40-

Javier D. Bruguera, Tomás Lang: Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. IEEE Symposium on Computer Arithmetic 2001: 203-210

José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller: FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation. DSD 2001: 262-269

Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera: Implementation of a NURBS to Bézier Conversor with Constant Latency. FPL 2001: 213-222

Juan Touriño, Francisco F. Rivera, Carlos Álvarez, Cesar M. Dans, Jorge Parapar, Ramon Doallo, Marcos Boullón, Javier D. Bruguera, Rafael Crecente, Xesús P. González: COPA: a GIS-based Tool for Land Consolidation Projects. ACM-GIS 2001: 53-58

José Carlos Mouriño, David E. Singh, María J. Martín, J. M. Eiroa, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera: Parallelization of the STEM-II Air Quality Model. HPCN Europe 2001: 543-546

José Carlos Mouriño, María J. Martín, Ramon Doallo, David E. Singh, Francisco F. Rivera, Javier D. Bruguera: The STEM-II Air Quality Model on a Distributed Memory System. ICPP Workshops 2001: 85-92

Elisardo Antelo, Tomás Lang, Javier D. Bruguera: Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. IEEE Trans. Computers 49(7): 727-739 (2000)

Elisardo Antelo, Tomás Lang, Javier D. Bruguera: Very-High Radix CORDIC Rotation Based on Selection by Rounding. VLSI Signal Processing 25(2): 141-153 (2000)

Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera: Parallel Architecture for Conversion of NURBS Curves to Bézier Curves. EUROMICRO 2000: 1324-1331

Javier D. Bruguera, Tomás Lang: Multilevel Reverse-Carry Adder. ICCD 2000: 155-162

Javier D. Bruguera, Tomás Lang: Leading-One Prediction with Concurrent Position Correction. IEEE Trans. Computers 48(10): 1083-1097 (1999)

Elisardo Antelo, Tomás Lang, Javier D. Bruguera: Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. IEEE Symposium on Computer Arithmetic 1999: 204-

Tomás Lang, Javier D. Bruguera: Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. ICCD 1999: 73-79

Elisardo Antelo, Tomás Lang, Javier D. Bruguera: Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling. IEEE Trans. Computers 47(2): 152-161 (1998)

Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata: A novel design of a two operand normalization circuit. IEEE Trans. VLSI Syst. 6(1): 173-176 (1998)

Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: Radix-4 Vectoring CORDIC Algorithm and Architectures. VLSI Signal Processing 19(2): 127-147 (1998)

Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera: Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. EUROMICRO 1998: 10139-

Javier D. Bruguera, Tomás Lang: Leading-one prediction scheme for latency improvement in single datapath floating-point adders. ICCD 1998: 298-305

Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata: High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers 46(8): 855-870 (1997)

Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Emilio L. Zapata: Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm. IEEE Trans. Computers 46(11): 1264-1271 (1997)

Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata: High-performance VLSI architecture for the Viterbi algorithm. IEEE Transactions on Communications 45(2): 168-176 (1997)

Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata: Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures. VLSI Signal Processing 17(1): 57-73 (1997)

Roberto R. Osorio, Javier D. Bruguera: New arithmetic coder/decoder architectures based on pipelining. ASAP 1997: 106-115

Mercedes Peón, Roberto R. Osorio, Javier D. Bruguera: A VLSI implementation of an arithmetic coder for image compression. EUROMICRO 1997: 591-

Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata: Unified Mixed Radix 2-4 Redundant CORDIC Processor. IEEE Trans. Computers 45(9): 1068-1073 (1996)

Javier D. Bruguera, Nicolas Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata: Cordic based parallel/pipelined architecture for the Hough transform. VLSI Signal Processing 12(3): 207-221 (1996)

Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP 1996: 55-64

Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata: High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. ASAP 1996: 165-

Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata: High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II 1996: 155-164

Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata: High performance VLSI architecture for the trellis coded quantization. ICIP (2) 1996: 995-998

Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata: A Parallel Architecture for the Self-Sorting FFT Algorithm. J. Parallel Distrib. Comput. 31(1): 88-97 (1995)

Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata: Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic 1995: 172-179

Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata: Digit On-line Large Radix CORDIC Rotator. ASAP 1995: 246-257

Julio Villalba, J. A. Hidalgo, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP 1995: 258-269

Francisco Argüello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata: Parallel Architecture for Fast Transforms with Trigonometric Kernel. IEEE Trans. Parallel Distrib. Syst. 5(10): 1091-1099 (1994)

Javier D. Bruguera, Elisardo Antelo, Emilio L. Zapata: Design of a Pipelined Radix 4 CORDIC Processor. Parallel Computing 19(7): 729-744 (1993)

Oscar G. Plata, Javier D. Bruguera, Francisco F. Rivera, Ramon Doallo, Emilio L. Zapata: ACLE: A Software Package for SIMD Computer Simulation. Comput. J. 33(3): 194-203 (1990)

Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera, Emilio L. Zapata, R. Peskin: Gaussian elimination with pivoting on hypercubes. Parallel Computing 14(1): 51-60 (1990)

Inmaculada García, Juan J. Merelo Guervós, Javier D. Bruguera, Emilio L. Zapata: Parallel quadrant interlocking factorization on hypercube computers. Parallel Computing 15(1-3): 87-100 (1990)