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John F. Bulzacchelli
2010 – today
- 2012
[j5]John F. Bulzacchelli, Zeynep Toprak Deniz, Todd M. Rasmus, Joseph A. Iadanza, William L. Bucossi, Seongwon Kim, Rafael Blanco, Carrie E. Cox, Mohak Chhabra, Christopher D. LeBlanc, Christian L. Trudeau, Daniel J. Friedman: Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage. J. Solid-State Circuits 47(4): 863-874 (2012)- [j4]Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman: An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. J. Solid-State Circuits 47(4): 884-896 (2012)
- [j3]Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli: A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. J. Solid-State Circuits 47(8): 1828-1841 (2012)
- [j2]Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman: A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. J. Solid-State Circuits 47(12): 3220-3231 (2012)
- [j1]John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, W. R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman: A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. J. Solid-State Circuits 47(12): 3232-3248 (2012)
- [c7]Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman: A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. ISSCC 2012: 134-136
- [c6]John F. Bulzacchelli, Troy J. Beukema, Daniel Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman: A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. ISSCC 2012: 324-326
- [c5]Franco Stellari, Thomas Cowell, Peilin Song, Michael Sorna, Zeynep Toprak Deniz, John F. Bulzacchelli, Nandita A. Mitra: Root cause identification of an hard-to-find on-chip power supply coupling fail. ITC 2012: 1-7
- 2011
- [c4]Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli: A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology. CICC 2011: 1-4
2000 – 2009
- 2009
- [c3]Alexander Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman: Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. ISSCC 2009: 94-95
- [c2]Yong Liu, Byungsub Kim, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman: A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. ISSCC 2009: 182-183
- [c1]John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman: A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. ISSCC 2009: 368-369
Coauthor Index
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last updated on 2013-04-09 21:28 CEST by the dblp team