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José V. Busquets-Mataix
J. V. Busquets
2010 – today
- 2011
[c9]José V. Busquets-Mataix, Carlos Catalá, Antonio Martí Campoy: Architecture Extensions for Efficient Management of Scratch-Pad Memory. PATMOS 2011: 43-52
2000 – 2009
- 2005
- [c8]Antonio Martí Campoy, Isabelle Puaut, Angel Perles Ivars, José V. Busquets-Mataix: Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison. ECRTS 2005: 49-56
- [c7]Antonio Martí Campoy, Eugenio Tamura, S. Sáez, Francisco Rodríguez, José V. Busquets-Mataix: On Using Locking Caches in Embedded Real-Time Systems. ICESS 2005: 150-159
- 2003
- [c6]Antonio Martí Campoy, S. Sáez, A. Perles, J. V. Busquets: Schedulability Analysis in EDF Scheduler with Cache Memories. RTCSA 2003: 328-341
- 2000
- [j2]José V. Busquets-Mataix, Daniel Gil, Pedro J. Gil, Andy J. Wellings: Techniques to increase the schedulable utilization of cache-based preemptive real-time systems. Journal of Systems Architecture 46(4): 357-378 (2000)
1990 – 1999
- 1999
- [j1]José Carlos Campelo, Francisco Rodríguez, Alicia Rubio, Rafael Ors, Pedro J. Gil, Lenin Lemus, J. V. Busquets, José Albaladejo, Juan José Serrano: Distributed industrial control systems: a fault-tolerant architecture. Microprocessors and Microsystems - Embedded Hardware Design 23(2): 103-112 (1999)
- [c5]Daniel Gil, R. Martínez, J. V. Busquets, Juan Carlos Baraza, Pedro J. Gil: Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System. EDCC 1999: 191-208
- 1998
- [c4]Daniel Gil, Juan Carlos Baraza, J. V. Busquets, Pedro J. Gil: Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System. EUROMICRO 1998: 10418-10425
- 1996
- [c3]José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings: Adding instruction cache effect to schedulability analysis of preemptive real-time systems. IEEE Real Time Technology and Applications Symposium 1996: 204-
- [c2]José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings: Using harmonic task-sets to increase the schedulable utilization of cache-based preemptive real-time systems. RTCSA 1996: 195-202
- 1995
- [c1]José V. Busquets-Mataix, Juan José Serrano: The impact of extrinsic cache performance on predictability of real-time systems. RTCSA 1995: 8-15
Coauthor Index
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last updated on 2012-12-02 21:02 CET by the dblp team