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 | 2013 | |
|---|---|---|
| c36 |      | |
| 2012 | ||
| c35 | | Jon T. Butler, Tsutomu Sasao: Hardware Index to Permutation Converter. IPDPS Workshops 2012: 431-436 |
| c34 | | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Analysis of Multi-state Systems with Multi-state Components Using EVMDDs. ISMVL 2012: 122-127 |
| 2011 | ||
| j32 | | Jon T. Butler, C. L. Frenzen, Njuguna Macaria, Tsutomu Sasao: A fast segmentation algorithm for piecewise polynomial numeric function generators. J. Computational Applied Mathematics 235(14): 4076-4082 (2011) |
| c33 | | |
| c32 | | |
| c31 | | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Numeric Function Generators Using Piecewise Arithmetic Expressions. ISMVL 2011: 16-21 |
| 2010 | ||
| j31 | | Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler: A Quaternary Decision Diagram Machine: Optimization of Its Code. IEICE Transactions 93-D(8): 2026-2035 (2010) |
| j30 | | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams. IEICE Transactions 93-D(8): 2059-2067 (2010) |
| j29 | | C. L. Frenzen, Tsutomu Sasao, Jon T. Butler: On the number of segments needed in a piecewise linear approximation. J. Computational Applied Mathematics 234(2): 437-446 (2010) |
| c30 | | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs. ISMVL 2010: 223-228 |
| 2009 | ||
| b1 | | Tsutomu Sasao, Jon T. Butler: Progress in Applications of Boolean Functions. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2009 |
| c29 | | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions. ISMVL 2009: 349-355 |
| c28 | | Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler: A Quaternary Decision Diagram Machine and the Optimization of its Code. ISMVL 2009: 362-369 |
| 2008 | ||
| c27 | | Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao: Programmable Numerical Function Generators for Two-Variable Functions. DSD 2008: 891-898 |
| c26 | | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Numerical function generators using bilinear interpolation. FPL 2008: 463-466 |
| 2007 | ||
| j28 | | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs. IEICE Transactions 90-A(12): 2752-2761 (2007) |
| j27 | | Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler: Numerical Function Generators Using LUT Cascades. IEEE Trans. Computers 56(6): 826-838 (2007) |
| c25 | | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. ASP-DAC 2007: 535-540 |
| c24 | | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. DSD 2007: 280-287 |
| 2006 | ||
| j26 | | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method. IEICE Transactions 89-A(12): 3510-3518 (2006) |
| c23 | | Hui Qin, Tsutomu Sasao, Jon T. Butler: Implementation of LPM Address Generators on FPGAs. ARC 2006: 170-181 |
| c22 | | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. ASP-DAC 2006: 378-383 |
| c21 | | Tsutomu Sasao, Jon T. Butler: Implementation of Multiple-Valued CAM Functions by LUT Cascades. ISMVL 2006: 11 |
| 2005 | ||
| j25 | | Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura: Average Path Length of Binary Decision Diagrams. IEEE Trans. Computers 54(9): 1041-1053 (2005) |
| c20 |  | Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler: Programmable Numerical Function Generators: Architectures and Synthesis Method. FPL 2005: 118-123 |
| 2004 | ||
| c19 | | Tsutomu Sasao, Jon T. Butler: A fast method to derive minimum SOPs for decomposable functions. ASP-DAC 2004: 585-590 |
| 2003 | ||
| c18 | | Jon T. Butler, Tsutomu Sasao: On the Average Path Length in Decision Diagrams of Multiple-Valued Functions. ISMVL 2003: 383-390 |
| 2001 | ||
| j24 | | Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko: On the number of generators for transeunt triangles. Discrete Applied Mathematics 108(3): 309-316 (2001) |
| j23 | | Tsutomu Sasao, Jon T. Butler: Worst and Best Irredundant Sum-of-Products Expressions. IEEE Trans. Computers 50(9): 935-948 (2001) |
| c17 | | Tsutomu Sasao, Jon T. Butler: On the minimization of SOPs for bi-decomposition functions. ASP-DAC 2001: 219-224 |
| 2000 | ||
| j22 | | Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich: Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1386-1388 (2000) |
| c16 | | Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko: Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ISMVL 2000: 141-146 |
| 1998 | ||
| c15 | | Jon T. Butler, Tsutomu Sasao: On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels. ISMVL 1998: 83-88 |
| 1997 | ||
| j21 | | Kriss A. Schueller, Jon T. Butler: Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits. IEEE Trans. Computers 46(2): 205-209 (1997) |
| j20 | | Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III: Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions. IEEE Trans. Computers 46(4): 491-494 (1997) |
| c14 | | Tsutomu Sasao, Jon T. Butler: Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions. ISMVL 1997: 55-60 |
| 1996 | ||
| c13 | | Jon T. Butler, J. L. Nowlin, Tsutomu Sasao: Planarity in ROMDD's of Multiple-Valued Symmetric Functions. ISMVL 1996: 236-241 |
| c12 | | Tsutomu Sasao, Jon T. Butler: A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams. ISMVL 1996: 248-254 |
| 1995 | ||
| c11 | | |
| 1994 | ||
| c10 | | Gerhard W. Dueck, Jon T. Butler: Multiple-Valued Logic Operations with Universal Literals. ISMVL 1994: 73-79 |
| c9 | | Tsutomu Sasao, Jon T. Butler: A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion. ISMVL 1994: 97-106 |
| c8 | | Jon T. Butler, Tsutomu Sasao: Multiple-Valued Combinational Circuits with Feedback. ISMVL 1994: 342-347 |
| 1993 | ||
| c7 | | Cem Yildirim, Jon T. Butler, Chyan Yang: Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing. ISMVL 1993: 17-23 |
| 1992 | ||
| j19 | | Kriss A. Schueller, Jon T. Butler: On the Design of Cost-Tables for Realizing Multiple-Valued Circuits. IEEE Trans. Computers 41(2): 178-189 (1992) |
| c6 | | Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler: Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL 1992: 66-74 |
| c5 | | Susan W. Butler, Jon T. Butler: Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991. ISMVL 1992: 372-379 |
| 1991 | ||
| j18 | | Parthasarathy P. Tirumalai, Jon T. Butler: Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. IEEE Trans. Computers 40(2): 167-177 (1991) |
| c4 | | Jon T. Butler, Kriss A. Schueller: Worst Case Number of Terms in Symmetric Multiple-Valued Functions. ISMVL 1991: 94-101 |
| c3 | | Young-hoon Chang, Jon T. Butler: The Design of Current Mode CMOS Multiple-Valued Circuits. ISMVL 1991: 130-138 |
| 1990 | ||
| j17 | | Jon T. Butler, Kriss A. Schueller: On the Equivalence of Cost Functions in the Design of Circuits by Costtable. IEEE Trans. Computers 39(6): 842-844 (1990) |
| j16 | | Joo-Kang Lee, Jon T. Butler: A Characterization of t/s-Diagnosability an Sequential t-Diagnosability in Designs. IEEE Trans. Computers 39(10): 1298-1304 (1990) |
| c2 | | John M. Yurchak, Jon T. Butler: HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays. ISMVL 1990: 144-152 |
| c1 | | Jon T. Butler, Hans G. Kerkhoff, Siep Onneweer: A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach. ISMVL 1990: 286-291 |
| 1989 | ||
| j15 | | Edward A. Bender, Jon T. Butler: On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions. IEEE Trans. Computers 38(1): 82-98 (1989) |
| 1988 | ||
| j14 | | Jon T. Butler: Multiple-Valued Logic - Guest Editor's Introduction. IEEE Computer 21(4): 13-15 (1988) |
| j13 | | |
| 1985 | ||
| j12 | | |
| 1982 | ||
| j11 | | Jon T. Butler: On the relationship between propagating context-dependent lindenmayer systems and cellular automata systems. Inf. Sci. 28(1): 63-67 (1982) |
| 1981 | ||
| j10 | | Jon T. Butler: Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms. IEEE Trans. Computers 30(8): 590-596 (1981) |
| 1980 | ||
| j9 | | Patrick E. White, Jon T. Butler: Synthesis of One-Dimensional Binary Scope-2 Flexible Cellular Systems from Initial Final Configuration Pairs. Information and Control 46(3): 241-256 (1980) |
| 1979 | ||
| j8 | | Jon T. Butler: Synthesis of One-Dimensional Binary Cellular Automata Systems from Composite Local Maps. Information and Control 43(3): 304-326 (1979) |
| j7 | | Jon T. Butler: Decomposable Maps in General Tessellation Structures. J. Comput. Syst. Sci. 18(1): 1-7 (1979) |
| 1978 | ||
| j6 | | Jon T. Butler: Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates. J. ACM 25(3): 481-498 (1978) |
| j5 | | |
| j4 | | Edward A. Bender, Jon T. Butler: Asymptotic Aproximations for the Number of Fanout-Free Functions. IEEE Trans. Computers 27(12): 1180-1183 (1978) |
| 1976 | ||
| j3 | | |
| 1975 | ||
| j2 | | Jon T. Butler: On the Number of Functions Realized by Cascades and Disjunctive Networks. IEEE Trans. Computers 24(7): 681-690 (1975) |
| 1974 | ||
| j1 | | Jon T. Butler: A Note on Cellular Automata Simulations. Information and Control 26(3): 286-295 (1974) |
Colors in the list of coauthors
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