Paulo F. Butzen

Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas: Design of CMOS logic gates with enhanced robustness against aging degradation. Microelectronics Reliability 52(9-10): 1822-1826 (2012)

John Keane, S. Venkatraman, Paulo F. Butzen, Chris H. Kim: An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. IEEE Trans. VLSI Syst. 19(5): 787-795 (2011)

Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas: Impact and optimization of lithography-aware regular layout in digital circuit design. ICCD 2011: 279-284

Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas: Area impact analysis of via-configurable regular fabric for digital integrated circuit design. SBCCI 2011: 103-108

Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas: Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits. J. Low Power Electronics 6(1): 192-200 (2010)

Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André Inácio Reis, Renato P. Ribas: Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits. Microelectronics Journal 41(4): 247-255 (2010)

Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas: Transistor network restructuring against NBTI degradation. Microelectronics Reliability 50(9-11): 1298-1303 (2010)

Paulo F. Butzen, André Inácio Reis, Renato P. Ribas: Routing Resistance Influence in Loading Effect on Leakage Analysis. PATMOS 2009: 317-325

Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas: Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. ACM Great Lakes Symposium on VLSI 2008: 407-410

Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas: Modeling and estimating leakage current in series-parallel CMOS networks. ACM Great Lakes Symposium on VLSI 2007: 269-274

Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas: Modeling Subthreshold Leakage Current in General Transistor Networks. ISVLSI 2007: 512-513

Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas: Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. PATMOS 2007: 474-484