Ney Calazans
List of publications from the DBLP Bibliography Server - FAQ
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 | 2012 | |
|---|---|---|
| c55 |      | Julian J. H. Pontes, Ney Calazans, Pascal Vivet: Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects. ASYNC 2012: 142-149 |
| c54 | | Julian J. H. Pontes, Ney Calazans, Pascal Vivet: An accurate Single Event Effect digital design flow for reliable system level design. DATE 2012: 224-229 |
| c53 | | Taciano Perez, Ney Laert Vilar Calazans, César A. F. De Rose: A preliminary study on system-level impact of persistent main memory. ISQED 2012: 84-90 |
| c52 | | Matheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans: Impact of C-elements in asynchronous circuits. ISQED 2012: 437-343 |
| c51 | | Carlos A. Petry, Eduardo Wächter, Guilherme M. Castilhos, Fernando Gehm Moraes, Ney Laert Vilar Calazans: A spectrum of MPSoC models for design space exploration and its use. RSP 2012: 30-35 |
| c50 | | Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans: Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes. SBCCI 2012: 1-6 |
| c49 | | Thiago R. da Rosa, Vivian Larrea, Ney Calazans, Fernando Gehm Moraes: Power consumption reduction in MPSoCs through DFS. SBCCI 2012: 1-6 |
| 2011 | ||
| j6 | | Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres: A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines. IEEE Design & Test of Computers 28(5): 62-71 (2011) |
| j5 | | César A. M. Marcon, Ney Calazans, Edson I. Moreno, Fernando Moraes, Fabiano Hessel, Altamiro Amadeu Susin: CAFES: A framework for intrachip application modeling and communication architecture design. J. Parallel Distrib. Comput. 71(5): 714-728 (2011) |
| c48 | | Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans: Adapting a C-element design flow for low power. ICECS 2011: 45-48 |
| c47 | | Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Arbitration and routing impact on NoC design. International Symposium on Rapid System Prototyping 2011: 193-198 |
| c46 | | Thiago R. da Rosa, Guilherme Guindani, Douglas de O. Cardoso, Ney Laert Vilar Calazans, Fernando Gehm Moraes: A self-adaptable distributed DFS scheme for NoC-based MPSoCs. SBCCI 2011: 203-208 |
| c45 | | Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans: A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. SoCC 2011: 99-104 |
| 2010 | ||
| j4 | | Ewerson Luiz de Souza Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Dynamic Task Mapping for MPSoCs. IEEE Design & Test of Computers 27(5): 26-35 (2010) |
| c44 | | Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans: Hermes-A - An Asynchronous NoC Router with Distributed Routing. PATMOS 2010: 150-159 |
| c43 | | Leonel Tedesco, Thiago R. da Rosa, Fabien Clermidy, Ney Calazans, Fernando Gehm Moraes: Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip. SBCCI 2010: 91-96 |
| c42 | | Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres: A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks. SBCCI 2010: 115-120 |
| c41 | | Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans: Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. SoCC 2010: 493-498 |
| 2009 | ||
| c40 | | Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans: Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. DATE 2009: 634-639 |
| c39 | | Everton Carara, Roberto P. de Oliveira, Ney Laert Vilar Calazans, Fernando Gehm Moraes: HeMPS - a Framework for NoC-based MPSoC Generation. ISCAS 2009: 1345-1348 |
| c38 | | Taciano A. Rodolfo, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. ReConFig 2009: 24-29 |
| c37 | | Guilherme Guindani, Frederico Ferlini, Jeferson Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, Fernando Gehm Moraes: A 10 Gbps OTN Framer Implementation Targeting FPGA Devices. ReConFig 2009: 30-35 |
| 2008 | ||
| j3 | | César Augusto Missio Marcon, Edson Ifarraguirre Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Comparison of network-on-chip mapping algorithms targeting low energy consumption. IET Computers & Digital Techniques 2(6): 471-482 (2008) |
| c36 | | Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans: Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ISVLSI 2008: 347-352 |
| c35 | | Guilherme Guindani, Cezar Reinbrecht, Thiago Raupp, Ney Calazans, Fernando Gehm Moraes: NoC Power Estimation at the RTL Abstraction Level. ISVLSI 2008: 475-478 |
| c34 | | Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans: Triple Rail Logic Robustness against DPA. ReConFig 2008: 415-420 |
| c33 | | Edson Ifarraguirre Moreno, Katalin Maria Popovici, Ney Laert Vilar Calazans, Ahmed Amine Jerraya: Integrating Abstract NoC Models within MPSoC Design. IEEE International Workshop on Rapid System Prototyping 2008: 65-71 |
| c32 | | Fernando Gehm Moraes, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans: MOTIM: an industrial application using nocs. SBCCI 2008: 182-187 |
| c31 | | Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert: Evaluating the robustness of secure triple track logic through prototyping. SBCCI 2008: 193-198 |
| 2007 | ||
| c30 | | Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans: SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. ICCD 2007: 541-546 |
| c29 | | César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Evaluation of Algorithms for Low Energy Mapping onto NoCs. ISCAS 2007: 389-392 |
| c28 | | Erico Bastos, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Moraes: MOTIM - A Scalable Architecture for Ethernet Switches. ISVLSI 2007: 451-452 |
| c27 | | Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. ISVLSI 2007: 459-460 |
| c26 |  | Leandro Möller, Ismael Grehs, Ewerson Carvalho, Rafael Soares, Ney Calazans, Fernando Moraes: A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. ReCoSoC 2007: 23-30 |
| c25 | | Luis Carlos Caruso, Guilherme Guindani, Hugo Schmitt, Ney Calazans, Fernando Moraes: SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems. IEEE International Workshop on Rapid System Prototyping 2007: 27-33 |
| c24 | | Ewerson Carvalho, Ney Calazans, Fernando Moraes: Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs. IEEE International Workshop on Rapid System Prototyping 2007: 34-40 |
| c23 | | Leonel Tedesco, Fernando Moraes, Ney Calazans: Buffer sizing for QoS flows in wormhole packet switching NoCs. SBCCI 2007: 99-104 |
| c22 | | Everton Carara, Fernando Moraes, Ney Calazans: Router architecture for high-performance NoCs. SBCCI 2007: 111-116 |
| c21 | | Aline Mello, Ney Laert Vilar Calazans: Rate-based scheduling policy for QoS flows in networks on chip. VLSI-SoC 2007: 140-145 |
| i2 | | César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel: Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. CoRR abs/0710.4738 (2007) |
| i1 | | Aline Mello, Leandro Möller, Ney Calazans, Fernando Moraes: MultiNoC: A Multiprocessing System Enabled by a Network on Chip. CoRR abs/0710.4843 (2007) |
| 2006 | ||
| c20 | | Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes: Reconfigurable Systems Enabled by a Network-on-Chip. FPL 2006: 1-4 |
| c19 | | Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes: Infrastructure for dynamic reconfigurable systems: choices and trade-offs. SBCCI 2006: 44-49 |
| c18 | | Leonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes: Application driven traffic modeling for NoCs. SBCCI 2006: 62-67 |
| 2005 | ||
| c17 | | Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes, Ney Calazans: MAIA: a framework for networks on chip generation and verification. ASP-DAC 2005: 49-52 |
| c16 | | César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel: Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. DATE 2005: 502-507 |
| c15 | | Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans: Energy and latency evaluation of NoC topologies. ISCAS (6) 2005: 5866-5869 |
| c14 | | César A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans: Models for Embedded Application Mapping onto NoCs: Timing Analysis. IEEE International Workshop on Rapid System Prototyping 2005: 17-23 |
| c13 | | Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes: Virtual channels in networks on chip: implementation and evaluation on hermes NoC. SBCCI 2005: 178-183 |
| c12 | | Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes: Traffic generation and performance evaluation for mesh-based NoCs. SBCCI 2005: 184-189 |
| c11 | | José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin: Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. SBCCI 2005: 196-201 |
| c10 | | César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis: Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. VLSI-SoC 2005: 179-194 |
| 2004 | ||
| j2 | | Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost: HERMES: an infrastructure for low area overhead packet-switching networks on chip. Integration 38(1): 69-93 (2004) |
| c9 | | Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes: MultiNoC: A Multiprocessing System Enabled by a Network on Chip. DATE 2004: 234-239 |
| c8 | | Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato: FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. FPL 2004: 1042-1046 |
| c7 | | Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes: PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems. SBCCI 2004: 10-15 |
| 2003 | ||
| c6 | | Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans: Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. DATE 2003: 11122-11123 |
| c5 | | Daniel Mesquita, Fernando Gehm Moraes, José Palma, Leandro Möller, Ney Laert Vilar Calazans: Remote and Partial Reconfiguration of FPGAs: Tools and Trends. IPDPS 2003: 177 |
| c4 | | Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara: From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. SBCCI 2003: 355- |
| c3 | | Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans: A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. VLSI-SOC 2003: 318-323 |
| 2002 | ||
| c2 | | César A. M. Marcon, Fabiano Hessel, Alexandre M. Amory, Luis H. L. Ries, Fernando Gehm Moraes, Ney Laert Vilar Calazans: Prototyping of embedded digital systems from SDL language: a case study. HLDVT 2002: 133-138 |
| 2001 | ||
| j1 | | Ney Laert Vilar Calazans, Fernando Gehm Moraes, Delfim Luiz Torok, Andrey V. Andreoli: Projeto para Prototipação de um IP Soft Core MAC Ethernet. RITA 8(1): 23-41 (2001) |
| 1994 | ||
| c1 | | Ney Laert Vilar Calazans: Boolean constrained encoding: a new formulation and a case study. ICCAD 1994: 702-706 |
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