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 | 2012 | |
|---|---|---|
| j12 |      | Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras: A reduced complexity scheme for carrier frequency synchronization in uplink 802.16e OFDMA. EURASIP J. Adv. Sig. Proc. 2012: 218 (2012) |
| j11 | | Ruzica Jevtic, Carlos Carreras: A complete dynamic power estimation model for data-paths in FPGA DSP designs. Integration 45(2): 172-185 (2012) |
| j10 | | Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras: Evaluation of Rapid Prototyping solutions for a 802.16d frequency Offset estimation Scheme. Journal of Circuits, Systems, and Computers 21(7) (2012) |
| c22 | | Pablo Barrio, Carlos Carreras, Roberto Sierra, Tobias Kenter, Christian Plessl: Turning control flow graphs into function calls: Code generation for heterogeneous architectures. HPCS 2012: 559-565 |
| 2011 | ||
| j9 | | Ruzica Jevtic, Carlos Carreras: Power Measurement Methodology for FPGA Devices. IEEE T. Instrumentation and Measurement 60(1): 237-247 (2011) |
| c21 | | Ruzica Jevtic, Bojan Jovanovic, Carlos Carreras: Power estimation of dividers implemented in FPGAs. ACM Great Lakes Symposium on VLSI 2011: 313-318 |
| c20 | | Pablo Barrio, Carlos Carreras: Mesh traversal and sorting for efficient memory usage in scientific codes. IPCCC 2011: 1-8 |
| 2010 | ||
| j8 | | Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero: SQNR Estimation of Fixed-Point DSP Algorithms. EURASIP J. Adv. Sig. Proc. 2010 (2010) |
| j7 | | Javier Gonzalez Bayon, Carlos Carreras, Ove Edfors: A Multistandard Frequency Offset Synchronization Scheme for 802.11n, 802.16d, LTE, and DVB-T/H Systems. Journal Comp. Netw. and Communic. 2010 (2010) |
| j6 | | Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras: Improved schemes for tracking residual frequency offset in DVB-T systems. IEEE Trans. Consumer Electronics 56(2): 415-422 (2010) |
| j5 | | Ruzica Jevtic, Carlos Carreras: Power Estimation of Embedded Multiplier Blocks in FPGAs. IEEE Trans. VLSI Syst. 18(5): 835-839 (2010) |
| c19 | | Gabriel Caffarena, Angel Fernandez Herrero, Juan A. López, Carlos Carreras: Fast Fixed-Point Optimization of DSP Algorithms. VLSI-SoC (Selected Papers) 2010: 182-205 |
| c18 | | Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero: Fast fixed-point optimization of DSP algorithms. VLSI-SoC 2010: 195-200 |
| c17 | | Gabriel Caffarena, Carlos Carreras: Architectural synthesis of DSP circuits under simultaneous error and time constraints. VLSI-SoC 2010: 322-327 |
| 2009 | ||
| j4 | | Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz: Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs. Int. J. Reconfig. Comp. 2009 (2009) |
| c16 | | Slobodan Bojanic, Vukasin Pejovic, Gabriel Caffarena, Vladimir Milovanovic, Carlos Carreras, Jelena Popovic: Behavioural Biometrics Hardware Based on Bioinformatics Matching. CISIS 2009: 171-178 |
| c15 | | Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras, Atta Badii: A Practical Method for Testing High-Speed Networking Hardware Architectures. ICNS 2009: 122-130 |
| c14 | | Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic: Floorplan-based FPGA interconnect power estimation in DSP circuits. SLIP 2009: 53-60 |
| 2008 | ||
| j3 | | Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz: Fast and accurate computation of the roundoff noise of linear time-invariant systems. IET Circuits, Devices & Systems 2(4): 393-408 (2008) |
| c13 | | Ruzica Jevtic, Carlos Carreras: Analytical High-Level Power Model for LUT-Based Components. PATMOS 2008: 369-378 |
| c12 | | Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz: Optimized Architectural Synthesis of Fixed-Point Datapaths. ReConFig 2008: 85-90 |
| c11 | | Ruzica Jevtic, Carlos Carreras, Domenik Helms: A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. ReConFig 2008: 361-366 |
| 2007 | ||
| j2 | | Gabriel Caffarena, Carlos E. Pedreira, Carlos Carreras, Slobodan Bojanic, Octavio Nieto-Taladriz: Fpga Acceleration for DNA Sequence Alignment. Journal of Circuits, Systems, and Computers 16(2): 245-266 (2007) |
| j1 | | Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz: Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1923-1933 (2007) |
| c10 | | Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena: Switching Activity Models for Power Estimation in FPGA Multipliers. ARC 2007: 201-213 |
| c9 |  | Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras: A TCP/IP Fragmentation Monitoring Core For Intrusion Prevention. ERSA 2007: 227-230 |
| c8 | | Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras: Adding Value to TCP/IP Based Information exchange Security by Specialized Hardware. SECURWARE 2007: 145-150 |
| 2006 | ||
| c7 | | Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz: High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. FPL 2006: 1-4 |
| 2004 | ||
| c6 | | Gerardo Leyva, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz: A Generator of High-Speed Floating-Point Modules. FCCM 2004: 306-307 |
| 2003 | ||
| c5 | | Juan A. López, Carlos Carreras, Gabriel Caffarena, Octavio Nieto-Taladriz: Fast characterization of the noise bounds derived from coefficient and signal quantization. ISCAS (4) 2003: 309-312 |
| 2000 | ||
| c4 | | Carlos Carreras, Manuel V. Hermenegildo: Grid-Based Histogram Arithmetic for the Probabilistic Analysis of Functions. SARA 2000: 107-123 |
| 1999 | ||
| c3 | | Carlos Carreras, Juan A. López, Octavio Nieto-Taladriz: Bit-Width Selection for Data-Path Implementations. ISSS 1999: 114-121 |
| 1996 | ||
| c2 | | Carlos Carreras, Juan Carlos López, María Luisa López Vallejo, Luis Sánchez, Carlos Delgado Kloos, Natividad Martínez Madrid: A Co-Design Methodology Based on Formal Specification and High-level Estimation. CODES 1996: 28-35 |
| 1994 | ||
| c1 | | Carlos Carreras, Carlos A. López, Manuel V. Hermenegildo: Analytic Model of a Cache Only Memory Architecture. PARLE 1994: 336-350 |
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