- CSB - MetaPress - Google - Bing - Yahoo
 | 2009 | |
|---|---|---|
| c6 |      | R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh: Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. ISQED 2009: 27-32 |
| 2006 | ||
| c5 | | R. Venkatraman, R. Castagnetti, S. Ramesh: The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability. ISQED 2006: 190-195 |
| 2005 | ||
| c4 | | R. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, Andres Teene, S. Ramesh: A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. ISQED 2005: 193-196 |
| c3 | | Andres Teene, Bob Davis, R. Castagnetti, J. Brown, S. Ramesh: Impact of Interconnect Process Variations on Memory Performance and Design. ISQED 2005: 694-699 |
| 2003 | ||
| c2 | | F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh: Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. ISQED 2003: 119-124 |
| 2001 | ||
| j1 |  | Helmut Puchner, Y.-C. Liu, W. Kong, F. Duan, R. Castagnetti: Substrate Engineering to Improve Soft-Error-Rate Immunity for SRAM Technologies. Microelectronics Reliability 41(9-10): 1319-1324 (2001) |
| 1994 | ||
| c1 | | Piero Malcovati, R. Castagnetti, Henry Baltes, Carlos Azeredo Leme, Franco Maloberti: Switched Capacitor Dual-Collector Magnetotransistors. ISCAS 1994: 595-598 |
Colors in the list of coauthors
Last update Wed May 22 10:54:56 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page