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Vincenzo Catania
2010 – today
- 2012
[j36]Maurizio Palesi, Rafael Tornero, Juan Manuel Orduña, Vincenzo Catania, Daniela Panno: Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach. J. UCS 18(7): 937-969 (2012)- [j35]Davide Patti, Andrea Spadaccini, Maurizio Palesi, Fabrizio Fazzino, Vincenzo Catania: Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator. IEEE Trans. Education 55(3): 406-411 (2012)
- [c54]Vincenzo Catania, Giuseppe La Torre, Salvatore Monteleone, Davide Patti, Stefano Vercelli, Fabio Ricciato: A Novel Approach to Web of Things: M2M and Enhanced Javascript Technologies. GreenCom 2012: 726-730
- [c53]Alessandro G. Di Nuovo, Giuseppe Ascia, Vincenzo Catania: A Study on Evolutionary Multi-Objective Optimization with Fuzzy Approximation for Computational Expensive Problems. PPSN (2) 2012: 102-111
- 2011
- [j34]Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. Appl. Soft Comput. 11(1): 382-398 (2011)
- [j33]Maurizio Palesi, Giuseppe Ascia, Fabrizio Fazzino, Vincenzo Catania: Data Encoding Schemes in Networks on Chip. IEEE Trans. on CAD of Integrated Circuits and Systems 30(5): 774-786 (2011)
- 2010
- [j32]Maurizio Palesi, Shashi Kumar, Vincenzo Catania: Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 426-440 (2010)
- [c52]Maurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania: An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. DSD 2010: 37-44
2000 – 2009
- 2009
- [j31]Maurizio Palesi, Shashi Kumar, Vincenzo Catania: Bandwidth-aware routing algorithms for networks-on-chip platforms. IET Computers & Digital Techniques 3(5): 413-429 (2009)
- [j30]Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: Application Specific Routing Algorithms for Networks on Chip. IEEE Trans. Parallel Distrib. Syst. 20(3): 316-330 (2009)
- [c51]Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania: Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. DSD 2009: 119-126
- [c50]Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Gianmarco De Francisci Morales: An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures. DSD 2009: 643-650
- [c49]Alessandro G. Di Nuovo, Santo Di Nuovo, Serafino Buono, Vincenzo Catania: Feedforward artificial neural network to estimate iq of mental retarded people from different psychometric instruments. IJCNN 2009: 690-696
- [c48]Alessandro G. Di Nuovo, Vincenzo Catania: Linguistic Modifiers to Improve the Accuracy-Interpretability Trade-Off in Multi-Objective Genetic Design of Fuzzy Rule Based Classifier Systems. ISDA 2009: 128-133
- 2008
- [j29]Alessandro G. Di Nuovo, Vincenzo Catania, Santo Di Nuovo, Serafino Buono: Psychology with soft computing: An integrated approach and its applications. Appl. Soft Comput. 8(1): 829-837 (2008)
- [j28]Vincenzo Catania, Maurizio Palesi, Davide Patti: Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems. TACO 5(2) (2008)
- [j27]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Trans. Computers 57(6): 809-820 (2008)
- [c47]Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania: Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. DSD 2008: 18-25
- [c46]Vincenzo Catania, Gianmarco De Francisci Morales, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: High Performance Computing for Embedded System Design: A Case Study. DSD 2008: 656-659
- [c45]Alessandro G. Di Nuovo, Vincenzo Catania: An evolutionary fuzzy c-means approach for clustering of bio-informatics databases. FUZZ-IEEE 2008: 2077-2082
- [c44]Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. NOCS 2008: 97-106
- 2007
- [j26]Vincenzo Catania, Maurizio Palesi, Davide Patti: Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario. Journal of Circuits, Systems, and Computers 16(5): 819-846 (2007)
- [j25]Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: Efficient design space exploration for application specific systems-on-a-chip. Journal of Systems Architecture 53(10): 733-750 (2007)
- [c43]Alessandro G. Di Nuovo, Maurizio Palesi, Vincenzo Catania: Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. FUZZ-IEEE 2007: 1-6
- [c42]Alessandro G. Di Nuovo, Vincenzo Catania: On External Measures for Validation of Fuzzy Partitions. IFSA (1) 2007: 491-501
- [c41]Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania: Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IPDPS 2007: 1-8
- 2006
- [j24]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. J. UCS 12(4): 370-394 (2006)
- [j23]Giuseppe Ascia, Vincenzo Catania, Daniela Panno: An integrated fuzzy-GA approach for buffer management. IEEE T. Fuzzy Systems 14(4): 528-541 (2006)
- [c40]Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: A methodology for design of application specific deadlock-free routing algorithms for NoC systems. CODES+ISSS 2006: 142-147
- [c39]Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania: Fuzzy decision making in embedded system design. CODES+ISSS 2006: 223-228
- [c38]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. ESTImedia 2006: 79-84
- [c37]Alessandro G. Di Nuovo, Vincenzo Catania, Santo Di Nuovo, Serafino Buono: Evolving Fuzzy C-Means: An intelligent technique for efficient diagnosis of children mental retardation level from databases with missing values. IC-AI 2006: 290-296
- [c36]Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. ICSAMOS 2006: 115-122
- [c35]Alessandro G. Di Nuovo, Vincenzo Catania: Genetic Tuning of Fuzzy Rule Deep Structures for Efficient Knowledge Extraction from Medical Data. SMC 2006: 5053-5058
- 2005
- [j22]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 635-645 (2005)
- [j21]Giuseppe Ascia, Vincenzo Catania, Daniela Panno: An evolutionary management scheme in high-performance packet switches. IEEE/ACM Trans. Netw. 13(2): 262-275 (2005)
- [c34]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Exploring Design Space of VLIW Architectures. ASAP 2005: 86-91
- [c33]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. ASP-DAC 2005: 940-943
- [c32]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: An evolutionary approach to network-on-chip mapping problem. Congress on Evolutionary Computation 2005: 112-119
- [c31]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Hyperblock formation: a power/energy perspective for high performance VLIW architectures. ISCAS (4) 2005: 4090-4093
- 2004
- [j20]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A GA-based design space exploration framework for parameterized system-on-a-chip platforms. IEEE Trans. Evolutionary Computation 8(4): 329-346 (2004)
- [c30]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: Multi-objective mapping for mesh-based NoC architectures. CODES+ISSS 2004: 182-187
- [c29]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Multi-objective Optimization of a Parameterized VLIW Architecture. Evolvable Hardware 2004: 191-198
- 2003
- [c28]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato: An evolutionary approach for reducing the switching activity in address buses. IEEE Congress on Evolutionary Computation (1) 2003: 107-114
- [c27]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. ESTImedia 2003: 65-72
- [c26]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato: An evolutionary approach for reducing the energy in address buses. ISICT 2003: 76-81
- [c25]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. PATMOS 2003: 21-30
- [c24]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Genetic Approach To Bus Encoding. VLSI-SOC 2003: 426-431
- 2002
- [c23]Giuseppe Ascia, Vincenzo Catania, Daniela Panno: An efficient buffer management policy based on an integrated Fuzzy-GA approach. INFOCOM 2002
- [c22]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Framework for Design Space Exploration of Parameterized VLSI Systems. VLSI Design 2002: 245-250
- 2001
- [j19]Vincenzo Catania, Giuseppe Ficili, Daniela Panno: An integrated framework for traffic control in ATM networks based on soft-computing techniques. Inf. Sci. 138(1-4): 31-44 (2001)
- [j18]Giuseppe Ascia, Vincenzo Catania, Daniela Panno: An efficient fuzzy system for traffic management in high-speed packet-switched networks. Soft Comput. 5(4): 247-256 (2001)
- [c21]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: Parameterised system design based on genetic algorithms. CODES 2001: 177-182
- [c20]Giuseppe Ascia, Vincenzo Catania: A General Purpose Processor Oriented Fuzzy Reasoning. FUZZ-IEEE 2001: 352-355
- [c19]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. VLSI-SOC 2001: 157-168
- [c18]Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Daniela Panno: A Fuzzy Buffer Management Scheme For ATM and IP Networks. INFOCOM 2001: 1539-1547
- [c17]Giuseppe Ascia, Vincenzo Catania, Daniela Panno: An adaptive fuzzy threshold scheme for high performance shared-memory switches. SAC 2001: 456-461
1990 – 1999
- 1999
- [j17]Vincenzo Catania, Giuseppe Ficili, Daniela Panno: On the impact of traffic control algorithms on resource management in ATM networks. Computer Communications 22(3): 258-265 (1999)
- [j16]Giuseppe Ascia, Vincenzo Catania, Marco Russo: VLSI hardware architecture for complex fuzzy systems. IEEE T. Fuzzy Systems 7(5): 553-570 (1999)
- [c16]Vincenzo Catania, Giuseppe Ficili, Daniela Panno: A Framework for Traffic Control in Integrated Services Networks Based on Fuzzy Logic. Applied Informatics 1999: 427-429
- [c15]Giuseppe Ascia, Vincenzo Catania: An Optimized Parallel RISC Processor for Fuzzy Computing. Applied Informatics 1999: 454-456
- 1998
- [c14]Giuseppe Ascia, Vincenzo Catania: A Framework for a Parallel Architecture Dedicated to Soft Computing. VLSI Design 1998: 318-321
- 1997
- [j15]Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Sergio Palazzo, Daniela Panno: A VLSI fuzzy expert system for real-time traffic control in ATM networks. IEEE T. Fuzzy Systems 5(1): 20-31 (1997)
- [c13]Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili: Design of a VLSI Hardware PET Decoder. VLSI Design 1997: 253-256
- 1996
- [j14]Vincenzo Catania, Antonio Puliafito, Salvatore Riccobene, Lorenzo Vita: Monitoring performance in distributed systems. Computer Communications 19(9-10): 788-803 (1996)
- [j13]Vincenzo Catania, Antonio Puliafito, Salvatore Riccobene, Lorenzo Vita: An I/O subsystem supporting mass storage functions in parallel systems. Computer Standards & Interfaces 18(2): 117-138 (1996)
- [j12]Giuseppe Ascia, Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: A Reconfigurable Parallel Architecture for a Fuzzy Processor. Inf. Sci. 88(1-4): 299-315 (1996)
- [j11]Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: A Fuzzy Approach to Mapping Problems. Inf. Sci. 95(3): 191-217 (1996)
- [j10]Vincenzo Catania, Giuseppe Ficili, Sergio Palazzo, Daniela Panno: A comparative analysis of fuzzy versus conventional policing mechanisms for ATM networks. IEEE/ACM Trans. Netw. 4(3): 449-459 (1996)
- 1995
- [j9]Vincenzo Catania, Giuseppe Ascia: A VLSI Parallel Architecture for Fuzzy Expert Systems. IJPRAI 9(2): 421-447 (1995)
- [j8]Vincenzo Catania, Antonio Puliafito, Salvatore Riccobene, Lorenzo Vita: Design and Performance Analysis of a Disk Array System. IEEE Trans. Computers 44(10): 1236-1247 (1995)
- [c12]Vincenzo Catania, N. Fiorito, Michele Malgeri, Marco Russo: A soft computing approach to hardware software codesign. Great Lakes Symposium on VLSI 1995: 158-163
- [c11]Vincenzo Catania, Giuseppe Ficili, Sergio Palazzo, Daniela Panno: A fuzzy decision maker for source traffic control in high speed networks. ICNP 1995: 136-143
- [c10]Vincenzo Catania, N. Fiorito, Michele Malgeri, Marco Russo: A Framework for Codesign Based on Fuzzy Logic and Genetic Algorithms. IEA/AIE 1995: 797-804
- [c9]
- [c8]Giuseppe Ascia, Vincenzo Catania: Design of a VLSI parallel processor for fuzzy computing. VLSI Design 1995: 315-320
- 1994
- [j7]Salvatore Casale, Vincenzo Catania, Aurelio La Corte: Service integration issues on an ATM DQDB MAN. Computer Communications 17(6): 407-418 (1994)
- [j6]Vincenzo Catania, Antonio Puliafito, Marco Russo, Lorenzo Vita: A VLSI fuzzy inference processor based on a discrete analog approach. IEEE T. Fuzzy Systems 2(2): 93-106 (1994)
- [c7]Vincenzo Catania, Antonio Puliafito, Salvatore Riccobene, Lorenzo Vita: Performance Evaluation of a Partial Dynamic Declustering Disk Array System. HPDC 1994: 244-252
- [c6]Vincenzo Catania, O. Granato, Antonio Puliafito, Lorenzo Vita: PMT: A Tool to Monitor Performances in Distributed Systems. HPDC 1994: 279-286
- 1993
- [j5]Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: A Model for Performance Evaluation of Gracefully Degrading Systems. Comput. J. 36(2): 177-185 (1993)
- [j4]Salvatore Casale, Vincenzo Catania, Aurelio La Corte, Lorenzo Vita: Service management on an ATM DQDB MAN. Computer Communications 16(3): 147-154 (1993)
- [j3]Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: High-speed data service in distributed systems based on SMDS. Computer Communications 16(7): 394-402 (1993)
- 1991
- [j2]Vincenzo Catania, Salvatore Cavalieri, Lorenzo Vita: Rearrangeable switch fabric for fast packet switching. Computer Communications 14(8): 451-460 (1991)
- [c5]Vincenzo Catania, L. Mazzola, Antonio Puliafito, Lorenzo Vita: Performance analysis of DQDB behaviour with priority levels. ICDCS 1991: 44-51
- [c4]Vincenzo Catania, Mario Gerla, Claudio Pavanelli: A Routing Strategy for MAN Interconnection. INFOCOM 1991: 608-615
- [c3]G. Marotta, M. Iudica, M. Tiraboschi, Vincenzo Catania, Lorenzo Vita, Andres Albanese, Tasco N. Devetzis, M. W. Maszczak: Internetworking data services. LCN 1991: 223-229
- 1990
- [c2]Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: Availability and Performability Assessment in LAN Interconnection. INFOCOM 1990: 1181-1187
1980 – 1989
- 1989
- [j1]Salvatore Casale, Vincenzo Catania, Alberto Faro, Nikolai Parchenkov, Lorenzo Vita: Design and performance evaluation of an optical fibre LAN with double token rings. Computer Communications 12(3): 158-166 (1989)
- [c1]Salvatore Casale, Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: A Multiple Spanning Tree Protocol in Bridged LANs. IFIP Congress 1989: 633-638
Coauthor Index
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last updated on 2013-05-22 20:49 CEST by the dblp team