Alessandro Cevrero

Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis: Fast and accurate BER estimation methodology for I/O links based on extreme value theory. DATE 2013: 503-508

Tiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse Kivilcim Coskun, Yusuf Leblebici: 3D-MMC: a modular 3D multi-core architecture with efficient resource pooling. DATE 2013: 1241-1246

Giulia Beanato, Paolo Giovannini, Alessandro Cevrero, Panagiotis Athanasopoulos, Michael Zervas, Yuksel Temiz, Yusuf Leblebici: Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 295-306 (2012)

Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici: Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. DAC 2011: 1014-1019

Christoph Roth, Alessandro Cevrero, Christoph Studer, Yusuf Leblebici, Andreas Burg: Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders. ISCAS 2011: 1772-1775

Fengda Sun, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici: Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs. VLSI-SoC 2010: 149-154

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed Hosein Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. TRETS 2(2) (2009)

Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne: A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219

Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne: FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. FCCM 2009: 267-270

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj: 3D configuration caching for 2D FPGAs. FPGA 2009: 286

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Using 3D integration technology to realize multi-context FPGAs. FPL 2009: 507-510

Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne: A flexible DSP block to enhance FPGA arithmetic performance. FPT 2009: 70-77

Jani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne: Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. SiPS 2009: 115-120

Seyed Hosein Attarzadeh Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Design space exploration for field programmable compressor trees. CASES 2008: 207-216

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190