Srimat T. Chakradhar

Abhinandan Majumdar, Srihari Cadambi, Michela Becchi, Srimat T. Chakradhar, Hans Peter Graf: A Massively Parallel, Energy Efficient Programmable Accelerator for Learning and Classification. TACO 9(1): 6 (2012)

Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan, T. N. Vijaykumar: Tarazu: optimizing MapReduce on heterogeneous clusters. ASPLOS 2012: 61-74

Vignesh T. Ravi, Michela Becchi, Wei Jiang, Gagan Agrawal, Srimat T. Chakradhar: Scheduling Concurrent Applications on a Cluster of CPU-GPU Nodes. CCGRID 2012: 140-147

Jun Liu, Nishkam Ravi, Srimat T. Chakradhar, Mahmut T. Kandemir: Panacea: towards holistic optimization of MapReduce applications. CGO 2012: 33-43

Reza Farivar, Anand Raghunathan, Srimat T. Chakradhar, Harshit Kharbanda, Roy H. Campbell: PIC: Partitioned Iterative Convergence for Clusters. CLUSTER 2012: 391-401

Michela Becchi, Kittisak Sajjapongse, Ian Graves, Adam M. Procter, Vignesh T. Ravi, Srimat T. Chakradhar: A virtual memory based runtime to support multi-tenancy in clusters with GPUs. HPDC 2012: 97-108

Rajat Phull, Cheng-Hong Li, Kunal Rao, Srihari Cadambi, Srimat T. Chakradhar: Interference-driven resource management for GPU-based heterogeneous clusters. HPDC 2012: 109-120

Nishkam Ravi, Yi Yang, Tao Bao, Srimat T. Chakradhar: Apricot: an optimizing compiler and productivity tool for x86-compatible many-core coprocessors. ICS 2012: 47-58

Haicheng Wu, Gregory F. Diamos, Jin Wang, Srihari Cadambi, Sudhakar Yalamanchili, Srimat T. Chakradhar: Optimizing Data Warehousing Applications for GPUs Using Kernel Fusion/Fission. IPDPS Workshops 2012: 2433-2442

Jacques A. Pienaar, Srimat T. Chakradhar, Anand Raghunathan: Automatic generation of software pipelines for heterogeneous parallel systems. SC 2012: 24

Vignesh T. Ravi, Michela Becchi, Gagan Agrawal, Srimat T. Chakradhar: ValuePack: value-based scheduling framework for CPU-GPU clusters. SC 2012: 53

Vishwani D. Agrawal, Srimat T. Chakradhar (Eds.): 25th International Conference on VLSI Design, VLSID 2012, Hyderabad, India, January 7-11, 2012. IEEE 2012, isbn 978-1-4673-0438-2

Abhinandan Majumdar, Srihari Cadambi, Srimat T. Chakradhar: An Energy-Efficient Heterogeneous System for Embedded Learning and Classification. Embedded Systems Letters 3(1): 42-45 (2011)

M. Mustafa Rafique, Srihari Cadambi, Kunal Rao, Ali Raza Butt, Srimat T. Chakradhar: Symphony: A Scheduler for Client-Server Applications on Coprocessor-Based Heterogeneous Clusters. CLUSTER 2011: 353-362

Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar: Dynamic effort scaling: managing the quality-efficiency tradeoff. DAC 2011: 603-608

M. Mustafa Rafique, Nishkam Ravi, Srihari Cadambi, Ali Raza Butt, Srimat T. Chakradhar: Power management for heterogeneous clusters: An experimental study. IGCC 2011: 1-8

Vignesh T. Ravi, Michela Becchi, Gagan Agrawal, Srimat T. Chakradhar: Supporting GPU sharing in cloud environments with a transparent runtime consolidation framework. HPDC 2011: 217-228

Dong Li, Surendra Byna, Srimat T. Chakradhar: Energy-Aware Workload Consolidation on GPU. ICPP Workshops 2011: 389-398

Jacques A. Pienaar, Anand Raghunathan, Srimat T. Chakradhar: MDR: performance model driven runtime for heterogeneous parallel platforms. ICS 2011: 225-234

Abhinandan Majumdar, Srihari Cadambi, Srimat T. Chakradhar, Hans Peter Graf: A parallel accelerator for semantic search. SASP 2011: 122-128

Lei Yang, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar: Online memory compression for embedded systems. ACM Trans. Embedded Comput. Syst. 9(3) (2010)

Lei Yang, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar: High-performance operating system controlled online memory compression. ACM Trans. Embedded Comput. Syst. 9(4) (2010)

Srihari Cadambi, Abhinandan Majumdar, Michela Becchi, Srimat T. Chakradhar, Hans Peter Graf: A programmable parallel accelerator for learning and classification. PACT 2010: 273-284

Surendra Byna, Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Srihari Cadambi: Best-effort semantic document search on GPUs. GPGPU 2010: 86-93

Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar: Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. DAC 2010: 555-560

Srimat T. Chakradhar, Anand Raghunathan: Best-effort computing: re-thinking parallel software and hardware. DAC 2010: 865-870

Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Surendra Byna: Exploiting the forgiving nature of applications for scalable parallel execution. IPDPS 2010: 1-12

Srimat T. Chakradhar, Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi: A dynamically configurable coprocessor for convolutional neural networks. ISCA 2010: 247-257

Michela Becchi, Surendra Byna, Srihari Cadambi, Srimat T. Chakradhar: Data-aware scheduling of legacy kernels on heterogeneous platforms with distributed memory. SPAA 2010: 82-91

Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi, Srimat T. Chakradhar, Igor Durdanovic, Eric Cosatto, Hans Peter Graf: A Massively Parallel Coprocessor for Convolutional Neural Networks. ASAP 2009: 53-60

Srihari Cadambi, Igor Durdanovic, Venkata Jakkula, Murugan Sankaradass, Eric Cosatto, Srimat T. Chakradhar, Hans Peter Graf: A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines. FCCM 2009: 115-122

Jiayuan Meng, Srimat T. Chakradhar, Anand Raghunathan: Best-effort parallel execution framework for Recognition and mining applications. IPDPS 2009: 1-12

Narayanan Sundaram, Anand Raghunathan, Srimat T. Chakradhar: A framework for efficient and scalable execution of domain-specific templates on GPUs. IPDPS 2009: 1-12

Janar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar: Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor. DATE 2008: 1148-1153

Nupur Kothari, Kiran Nagaraja, Vijay Raghunathan, Florin Sultan, Srimat T. Chakradhar: HERMES: A Software Architecture for Visibility and Control in Wireless Sensor Network Deployments. IPSN 2008: 395-406

Hans Peter Graf, Srihari Cadambi, Igor Durdanovic, Venkata Jakkula, Murugan Sankaradass, Eric Cosatto, Srimat T. Chakradhar: A Massively Parallel Digital Learning Processor. NIPS 2008: 529-536

Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar: Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. IEEE Trans. VLSI Syst. 15(6): 699-710 (2007)

Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar: Unknown blocking scheme for low control data volume and high observability. DATE 2007: 33-38

Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei: A hybrid scheme for compacting test responses with unknown values. ICCAD 2007: 513-519

Seongmoon Wang, Zhanglei Wang, Wenlong Wei, Srimat T. Chakradhar: A low cost test data compression technique for high n-detection fault coverage. ITC 2007: 1-10

Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell: Zero Cost Test Point Insertion Technique for Structured ASICs. VLSI Design 2007: 357-363

Seongmoon Wang, Srimat T. Chakradhar: A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1555-1564 (2006)

Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar: Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2193-2206 (2006)

Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar: A design methodology for application-specific networks-on-chip. ACM Trans. Embedded Comput. Syst. 5(2): 263-280 (2006)

Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar: Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. DAC 2006: 496-501

Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei: Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. DAC 2006: 1083-1088

Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar: Efficient unknown blocking using LFSR reseeding. DATE 2006: 1051-1052

Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng: Coverage loss by using space compactors in presence of unknown values. DATE 2006: 1053-1054

Jahangir Hasan, Srihari Cadambi, Venkata Jakkula, Srimat T. Chakradhar: Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture. ISCA 2006: 203-215

Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar: Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems. VLSI Design 2006: 639-644

Kedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar: PIDISC: Pattern Independent Design Independent Seed Compression Technique. VLSI Design 2006: 811-817

Tiehan Lv, Jiang Xu, Wayne Wolf, Burak Ozer, Jörg Henkel, Srimat T. Chakradhar: A Methodology for Architectural Design of Multimedia Multiprocessor SoCs. IEEE Design & Test of Computers 22(1): 18-26 (2005)

Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: SECA: security-enhanced communication architecture. CASES 2005: 78-89

Lei Yang, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar: CRAMES: compressed RAM for embedded systems. CODES+ISSS 2005: 93-98

Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng: Response shaper: a novel technique to enhance unknown tolerance for output response compaction. ICCAD 2005: 80-87

Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng: ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. ICCD 2005: 147-152

Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar: H.264 HDTV Decoder Using Application-Specific Networks-On-Chip. ICME 2005: 1508-1511

Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar: A methodology for design, modeling, and analysis of networks-on-chip. ISCAS (2) 2005: 1778-1781

Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar: XWRC: externally-loaded weighted random pattern testing for input test data compression. ITC 2005: 10

Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar: Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design 2005: 65-70

Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar: A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems. VLSI Design 2005: 117-123

Wei Li, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy: Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. VLSI Design 2005: 471-478

Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar: Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. VLSI Design 2005: 579-585

Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula: Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems. IEEE Design & Test of Computers 21(5): 406-415 (2004)

Seongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan: Re-configurable embedded core test protocol. ASP-DAC 2004: 234-237

Srimat T. Chakradhar: Open architecture test system: not why but when! ASP-DAC 2004: 337-340

Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv: A Case Study in Networks-on-Chip Design for Embedded Video. DATE 2004: 770-777

Seongmoon Wang, Xiao Liu, Srimat T. Chakradhar: Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets. DATE 2004: 1296-1301

Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: Tamper Resistance Mechanisms for Secure, Embedded Systems. VLSI Design 2004: 605-

Jörg Henkel, Wayne Wolf, Srimat T. Chakradhar: On-chip networks: A scalable, communication-centric embedded system design paradigm. VLSI Design 2004: 845-

Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula, Murugan Sankaradass: CoCo: a hardware/software platform for rapid prototyping of code compression technologies. DAC 2003: 306-311

Seongmoon Wang, Srimat T. Chakradhar: A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs. ITC 2003: 574-583

Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: Embedding Security in Wireless Embedded Systems. VLSI Design 2003: 269-270

Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: Efficient RTL Power Estimation for Large Designs. VLSI Design 2003: 431-439

Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar: Accurate Power Macro-modeling Techniques for Complex RTL Circuits. VLSI Design 2001: 235-241

Michael S. Hsiao, Srimat T. Chakradhar: Test Set Compaction Using Relaxed Subsequence Removal. J. Electronic Testing 16(4): 319-327 (2000)

Michael S. Hsiao, Srimat T. Chakradhar: Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits. J. Electronic Testing 16(4): 329-338 (2000)

Surendra Bommu, Kiran B. Doreswamy, Srimat T. Chakradhar: A Practical Vector Restoration Technique for Large Sequential Circuits. J. Electronic Testing 16(5): 521-539 (2000)

Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Cheng: Testable Path Delay Fault Cover for Sequential Circuits. J. Inf. Sci. Eng. 16(5): 673-686 (2000)

Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy: Resource-Constrained Compaction of Sequential Circuit Test Sets. VLSI Design 2000: 398-405

Srimat T. Chakradhar, Sujit Dey: Resynthesis and retiming for optimum partial scan. IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 621-630 (1999)

Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar: Primitive delay faults: identification, testing, and design for testability. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 669-684 (1999)

Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar: Testing High Speed VLSI Devices Using Slower Testers. VTS 1999: 16-21

Michael S. Hsiao, Srimat T. Chakradhar: Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits. Asian Test Symposium 1998: 452-457

Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy: Vector Restoration Using Accelerated Validation and Refinement. Asian Test Symposium 1998: 458-466

Michael S. Hsiao, Srimat T. Chakradhar: State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits. DATE 1998: 577-582

Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy: Static compaction using overlapped restoration and segment pruning. ICCAD 1998: 140-146

Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy: Static test sequence compaction based on segment reordering and accelerated vector restoration. ITC 1998: 954-961

Arun Balakrishnan, Srimat T. Chakradhar: Peripheral Partitioning and Tree Decomposition for Partial Scan. VLSI Design 1998: 181-186

Srimat T. Chakradhar, Anand Raghunathan: Bottleneck removal algorithm for dynamic compaction in sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1157-1172 (1997)

Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal: Redundancy removal and test generation for circuits with non-Boolean primitives. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1370-1377 (1997)

Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar: Design for Primitive Delay Fault Testability. ITC 1997: 436-445

Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler: Deriving Signal Constraints to Accelerate Sequential Test Generation. VLSI Design 1997: 488-494

Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar: Initialization issues in asynchronous circuit synthesis. J. Electronic Testing 9(3): 237-250 (1996)

Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan: Synthesis of initializable asynchronous circuits. IEEE Trans. VLSI Syst. 4(2): 254-263 (1996)

Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar: Identification and Test Generation for Primitive Faults. ITC 1996: 423-432

Arun Balakrishnan, Srimat T. Chakradhar: Sequential Circuits with combinational Test Generation Complexity. VLSI Design 1996: 111-117

Anand Raghunathan, Srimat T. Chakradhar: Dynamic test Sequence compaction for Sequential Circuits. VLSI Design 1996: 170-173

Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy: Synchronous Test Generation Model for Asynchronous Circuits. VLSI Design 1996: 178-185

Arun Balakrishnan, Srimat T. Chakradhar: Retiming with logic duplication transformation: theory and an application to partial scan. VLSI Design 1996: 296-302

Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal: An exact algorithm for selecting partial scan flip-flops. J. Electronic Testing 7(1-2): 83-93 (1995)

Sujit Dey, Srimat T. Chakradhar: Design of testable sequential circuits by repositioning flip-flops. J. Electronic Testing 7(1-2): 105-114 (1995)

Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal: Energy models for delay testing. IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 728-739 (1995)

Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: Test function embedding algorithms with application to interconnected finite state machines. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1115-1127 (1995)

Vishwani D. Agrawal, Srimat T. Chakradhar: Combinational ATPG theorems for identifying untestable faults in sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1155-1160 (1995)

Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A partition and resynthesis approach to testable design of large circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1268-1276 (1995)

Arun Balakrishnan, Srimat T. Chakradhar: Software transformations for sequential test generation. Asian Test Symposium 1995: 266-

Srimat T. Chakradhar, Anand Raghunathan: Bottleneck removal algorithm for dynamic compaction and test cycles reduction. EURO-DAC 1995: 98-104

Anand Raghunathan, Srimat T. Chakradhar: Acceleration techniques for dynamic vector compaction. ICCAD 1995: 310-317

Srimat T. Chakradhar: Optimum retiming of large sequential circuits. VLSI Design 1995: 135-140

Arun Balakrishnan, Srimat T. Chakradhar: Partial scan design for technology mapped circuits. VLSI Design 1995: 283-287

Srimat T. Chakradhar, Steven G. Rothweiler: Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. VTS 1995: 12-19

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Energy minimization and design for testability. J. Electronic Testing 5(1): 57-66 (1994)

Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal: An Exact Algorithm for Selecting Partial Scan Flip-Flops. DAC 1994: 81-86

Srimat T. Chakradhar, Sujit Dey: Resynthesis and Retiming for Optimum Partial Scan. DAC 1994: 87-93

Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan: Signal Transition Graph Transformations for Initializability. EDAC-ETC-EUROASIC 1994: 670

Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan: Initialization Isuues in the Synthesis of Asynchronous Circuits. ICCD 1994: 447-452

Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A Test Function Architecture for Interconnected Finite State Machines. VLSI Design 1994: 113-116

Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan: Synthesis of Initializable Asynchronous Circuits. VLSI Design 1994: 383-388

Sujit Dey, Srimat T. Chakradhar: Retiming sequential circuits to enhance testability. VTS 1994: 28-33

Igor Rivin, Srimat T. Chakradhar: Discrete test generation by continuous methods. VTS 1994: 100-105

Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal: Finite state machine synthesis with fault tolerant test function. J. Electronic Testing 4(1): 57-69 (1993)

Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler: A transitive closure algorithm for test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1015-1028 (1993)

Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler: Sequential Circuit Delay optimization Using Global Path Delays. DAC 1993: 483-489

Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A Synthesis Approach to Design for Testability. ITC 1993: 754-763

Srimat T. Chakradhar, Michael L. Bushnell: A solvable class of quadratic 0-1 programming. Discrete Applied Mathematics 36(3): 233-251 (1992)

Vishwani D. Agrawal, Srimat T. Chakradhar: Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems. IEEE Trans. Parallel Distrib. Syst. 3(6): 739-746 (1992)

Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal: Finite State Machine Synthesis with Fault Tolerant Test Function. DAC 1992: 562-567

Srimat T. Chakradhar, Vishwani D. Agrawal: A Transitive Closure Based Algorithm for Test Generation. DAC 1991: 353-358

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong: Neural Net and Boolean Satisfiability Models of Logic Circuits. IEEE Design & Test of Computers 7(5): 54-57 (1990)

Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal: Toward massively parallel automatic test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 981-994 (1990)

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Automatic Test Generation Using Quadratic 0-1 Programming. DAC 1990: 654-659

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Polynomial time solvable fault detection problems. FTCS 1990: 56-63

Vishwani D. Agrawal, Srimat T. Chakradhar: Logic Simulation and Parallel Processing. ICCAD 1990: 496-499

Vishwani D. Agrawal, Srimat T. Chakradhar: Performance estimation in a massively parallel system. SC 1990: 306-313