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Wang Jiang Chau
2010 – today
- 2013
[j5]Edgar Leonardo Romero, Marius Strum, Wang Jiang Chau: Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification. J. Electronic Testing 29(2): 223-236 (2013)- 2012
- [j4]Johanna Sepúlveda, Ricardo Pires, Guy Gogniat, Wang Jiang Chau, Marius Strum: QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection. Int. J. Reconfig. Comp. 2012 (2012)
- [c14]Martha Johanna Sepúlveda, Wang Jiang Chau, Marius Strum, César Pedraza, Guy Gogniat, Ricardo Pires: Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping. GECCO (Companion) 2012: 1449-1450
- [c13]Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Wang Jiang Chau, Marius Strum: Hybrid-on-chip communication architecture for dynamic MP-SoC protection. SBCCI 2012: 1-6
- [c12]A. Patino A. Gustavo, Jorge Gonzalez, Wang Jiang Chau, Marius Strum: Workload and task characterization based on operation modes timing analysis. SoCC 2012: 248-253
- 2011
- [j3]Carlos Ivan Castro Marquez, Edgar Leonardo Romero Tobar, Marius Strum, Wang Jiang Chau: A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling. J. Electronic Testing 27(4): 485-503 (2011)
- [c11]Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Wang Jiang Chau, Marius Strum: Dynamic NoC-based architecture for MPSoC security implementation. SBCCI 2011: 197-202
- 2010
- [j2]Johanna Sepúlveda, Ricardo Pires, Marius Strum, Wang Jiang Chau: Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection. Transactions on Computational Science 10: 187-201 (2010)
- [c10]Johanna Sepúlveda, Marius Strum, Wang Jiang Chau, Ricardo Pires: The LRD traffic impact on the NoC-based SoCs. SBCCI 2010: 97-102
2000 – 2009
- 2009
- [c9]Raul Acosta Hernandez, Marius Strum, Wang Jiang Chau, Jose Artur Quilici Gonzalez: The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training. IJCNN 2009: 1221-1228
- [c8]Carlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau: A PD-based methodology to enhance efficiency in testbenches with random stimulation. SBCCI 2009
- 2007
- [c7]Frederico De Faria, Marius Strum, Wang Jiang Chau: A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling. ISVLSI 2007: 265-272
- 2005
- [c6]Edgar Leonardo Romero, Marius Strum, Wang Jiang Chau: Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor. CODES+ISSS 2005: 327-332
- [c5]John Esquiagola, Guilherme Ozari, Marcio Yukio Teruya, Marius Strum, Wang Jiang Chau: A Dynamically Reconfigurable Bluetooth Base Band Unit. FPL 2005: 148-152
- [c4]Duarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau: Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI 2005: 56-61
- 2003
- [j1]Duarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau, W. C. Cunha: Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems. Microelectronics Reliability 43(2): 209-215 (2003)
1990 – 1999
- 1999
- [c3]Marcio Yukio Teruya, Marius Strum, Wang Jiang Chau: Architectural Transformations for Hierarchical Algorithmic Descriptions. VLSI 1999: 473-484
- 1998
- [c2]Paulo Sérgio Cardoso, Marius Strum, José Roberto de A. Amazonas, Wang Jiang Chau: A Methodology for Minimum Area Cellular Automata Generation. Asian Test Symposium 1998: 33-
- 1995
- [c1]Wang Jiang Chau, Edward P. Stabler: Collective Test Generation and Test Set Compaction. ISCAS 1995: 2008-2011
Coauthor Index
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last updated on 2013-04-24 23:04 CEST by the dblp team