Chia-I Chen

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	2012
j3		Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou: Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Transactions 95-A(2): 559-566 (2012)
	2011
j2		Juinn-Dar Huang, Chia-I Chen, Yen-Ting Lin, Wan-Ling Hsu: Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture. IEICE Transactions 94-A(4): 1151-1155 (2011)
c3		Chia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang: Architectural exploration of 3D FPGAs towards a better balance between area and delay. DATE 2011: 587-590
c2		Chia-I Chen, Juinn-Dar Huang: Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family. ISVLSI 2011: 369-370
	2010
j1		Chia-I Chen, Juinn-Dar Huang: A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication. IEICE Transactions 93-A(7): 1300-1308 (2010)
	2009
c1		Chia-I Chen, Juinn-Dar Huang: CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. ASP-DAC 2009: 67-72

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Last update Sun May 26 08:06:53 2013 CET by the DBLP Team —

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