Hung-Ming Chen

Hung-Ming Chen, Chuan-Chien Hou, Yu-Hsiang Wang: A 3D visualized expert system for maintenance and management of existing building facilities using reliability-based method. Expert Syst. Appl. 40(1): 287-299 (2013)

Ching-Yu Chin, Chung-Yi Kuan, Tsung-Ying Tsai, Hung-Ming Chen, Yoji Kajitani: Escaped Boundary Pins Routing for High-Speed Boards. IEEE Trans. on CAD of Integrated Circuits and Systems 32(3): 381-391 (2013)

Ren-Jie Lee, Hung-Ming Chen: A study of row-based area-array I/O design planning in concurrent chip-package design flow. ACM Trans. Design Autom. Electr. Syst. 18(2): 30 (2013)

Shih-Ying Sean Liu, Chieh-Jui Lee, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee: Effective power network prototyping via statistical-based clustering and sequential linear programming. DATE 2013: 1701-1706

Shih-Ying Sean Liu, Ren-Guo Luo, Hung-Ming Chen: A network-flow based algorithm for power density mitigation at post-placement stage. DATE 2013: 1707-1710

Po-Cheng Pan, Hung-Ming Chen, Chien-Chih Lin: PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design. DATE 2013: 1849-1854

Hung-Ming Chen: On the way to practical tools for beyond die codesign and integration. ISPD 2013: 61

Min-Yuan Cheng, Kuo-Yu Huang, Hung-Ming Chen: K-means particle swarm optimization with embedded chaotic search for solving multidimensional problems. Applied Mathematics and Computation 219(6): 3091-3099 (2012)

Hung-Ming Chen, Wei-Ko Kao, Hsing-Chih Tsai: Genetic programming for predicting aseismic abilities of school buildings. Eng. Appl. of AI 25(6): 1103-1113 (2012)

Hung-Ming Chen, Jung-Wen Lo, Chang-Kuo Yeh: An Efficient and Secure Dynamic ID-based Authentication Scheme for Telecare Medical Information Systems. J. Medical Systems 36(6): 3907-3915 (2012)

Min-Yuan Cheng, Kuo-Yu Huang, Hung-Ming Chen: Dynamic guiding particle swarm optimization with embedded chaotic search for solving multidimensional problems. Optimization Letters 6(4): 719-729 (2012)

Suradeth Aroonsantidecha, Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen: A fast thermal aware placement with accurate thermal analysis based on Green function. ASP-DAC 2012: 425-430

Shih-Ying Liu, Chieh-Jui Lee, Hung-Ming Chen: Agglomerative-based flip-flop merging with signal wirelength optimization. DATE 2012: 1391-1396

Hsin-Wu Hsu, Meng-Ling Chen, Hung-Ming Chen, Hung-Chun Li, Shi-Hao Chen: On effective flip-chip routing via pseudo single redistribution layer. DATE 2012: 1597-1602

Po-Cheng Pan, Hung-Ming Chen, Yi-Kan Cheng, Jill Liu, Wei-Yi Hu: Configurable analog routing methodology via technology and design constraint unification. ICCAD 2012: 620-626

Yeh-Chi Chang, Chun-Kai Wang, Hung-Ming Chen: On construction low power and robust clock tree via slew budgeting. ISPD 2012: 129-136

Chieh-Jui Lee, Shih-Ying Liu, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee: Hierarchical power network synthesis for multiple power domain designs. ISQED 2012: 477-482

Wei-Ko Kao, Hung-Ming Chen, Jui-Sheng Chou: Aseismic ability estimation of school building using predictive data mining models. Expert Syst. Appl. 38(8): 10252-10263 (2011)

Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits. J. Inf. Sci. Eng. 27(1): 287-302 (2011)

Chia-Yi Lin, Hung-Ming Chen: A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost Reduction. J. Inf. Sci. Eng. 27(6): 1943-1957 (2011)

Ren-Jie Lee, Hung-Ming Chen: Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign. IEEE Trans. VLSI Syst. 19(5): 904-909 (2011)

Ren-Jie Lee, Hung-Ming Chen: Row-based area-array I/O design planning in concurrent chip-package design flow. ASP-DAC 2011: 837-842

Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani: On routing fixed escaped boundary pins for high speed boards. DATE 2011: 461-466

Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen: Fast analog layout prototyping for nanometer design migration. ICCAD 2011: 517-522

Chuan-Pin Lu, Jui-Pin Li, Wei-Yi Liou, Hung-Ming Chen: The Development of Smart Assistive Technology Devices for Urinary Catheterization Monitoring. ICGEC 2011: 41-44

Meng-Chen Wu, Hung-Ming Chen, Jing-Yang Jou: Mixed non-rectangular block packing for non-Manhattan layout architectures. ISQED 2011: 257-262

Chang-Cheng Tsai, Tzu-Hen Lin, Shin-Han Tsai, Hung-Ming Chen: Clock planning for multi-voltage and multi-mode designs. ISQED 2011: 654-658

Kuo-Hsuan Meng, Po-Cheng Pan, Hung-Ming Chen: Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping. ISQED 2011: 777-784

Yi-Rong Chen, Hung-Ming Chen, Shih-Ying Liu: TSV-based 3D-IC placement for timing optimization. SoCC 2011: 290-295

Sheng-Fu Liang, Hung-Ming Chen, Yi-Che Liu: Image Enlargement by Applying Coordinate Rotation and Kernel Stretching to Interpolation Kernels. EURASIP J. Adv. Sig. Proc. 2010 (2010)

Chia-Yi Lin, Li-Chung Hsu, Hung-Ming Chen: On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques. IEICE Transactions 93-C(3): 369-378 (2010)

Chia-Yi Lin, Hsiu-Chuan Lin, Hung-Ming Chen: On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes. IEEE Trans. VLSI Syst. 18(8): 1220-1224 (2010)

Fang-Yu Fan, Hung-Ming Chen, I-Min Liu: Technology mapping with crosstalk noise avoidance. ASP-DAC 2010: 319-324

Chia-Yi Lin, Hung-Ming Chen: A novel two-dimensional scan-control scheme for test-cost reduction. ISQED 2010: 237-243

Houng-Yi Li, Iris Hui-Ru Jiang, Hung-Ming Chen: Simultaneous voltage island generation and floorplanning. SoCC 2010: 219-223

Meng-Chen Wu, Ming-Ching Lu, Hung-Ming Chen, Jing-Yang Jou: Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning. ACM Trans. Design Autom. Electr. Syst. 15(1) (2009)

Ren-Jie Lee, Hung-Ming Chen: Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign. IEEE Trans. VLSI Syst. 17(8): 1087-1098 (2009)

Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih: Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. DATE 2009: 845-850

Bo-Zhou Chen, Hung-Ming Chen, Li-Da Huang, Po-Cheng Pan: A stochastic-based efficient critical area extractor on OpenAccess platform. ACM Great Lakes Symposium on VLSI 2009: 197-202

Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang: Buffer/flip-flop block planning for power-integrity-driven floorplanning. ISQED 2009: 488-493

Hung-Ming Chen, Yu-Chin Lin: Web-FEM: An internet-based finite-element analysis framework with 3D graphics and parallel computing environment. Advances in Engineering Software 39(1): 55-68 (2008)

Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning. J. Inf. Sci. Eng. 24(1): 115-127 (2008)

Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: Effective decap insertion in area-array SoC floorplan design. ACM Trans. Design Autom. Electr. Syst. 13(4) (2008)

Lun-Chun Wei, Hung-Ming Chen, Li-Da Huang, Sarah Songjie Xu: Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow. ACM Great Lakes Symposium on VLSI 2008: 359-362

Bruce Tseng, Hung-Ming Chen: Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations. ISPD 2008: 23-30

Ming-Fang Lai, Hung-Ming Chen: An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign. ISQED 2008: 604-607

Wen-Lin Huang, Hung-Ming Chen, Shiow-Fen Hwang, Shinn-Ying Ho: Accurate prediction of enzyme subfamily class using an adaptive fuzzy k-nearest neighbor method. Biosystems 90(2): 405-413 (2007)

Hung-Ming Chen, Bo-Fu Liu, Hui-Ling Huang, Shiow-Fen Hwang, Shinn-Ying Ho: SODOCK: Swarm optimization for highly flexible protein-ligand docking. Journal of Computational Chemistry 28(2): 612-623 (2007)

Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. ASP-DAC 2007: 792-797

Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen: Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign. ASP-DAC 2007: 804-809

Chia-Yi Lin, Hung-Ming Chen: A selective pattern-compression scheme for power and test-data reduction. ICCAD 2007: 520-525

Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu: Using power gating techniques in area-array SoC floorplan design. SoCC 2007: 233-236

Po-Hung Chen, Hung-Ming Chen, Kuo-Jui Hung, Wen-Hsien Fang, Mon-Chau Shie, Feipei Lai: Markov model fuzzy-reasoning based algorithm for fast block motion estimation. J. Visual Communication and Image Representation 17(1): 131-142 (2006)

Hung-Ming Chen, I-Min Liu, Martin D. F. Wong: I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2552-2556 (2006)

Li-Chung Hsu, Hung-Ming Chen: On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design. ISQED 2006: 451-456

Shinn-Ying Ho, Chih-Hung Hsieh, Kuan-Wei Chen, Hui-Ling Huang, Hung-Ming Chen, Shinn-Jang Ho: Scoring Method for Tumor Prediction from Microarray Data Using an Evolutionary Fuzzy Classifier. PAKDD 2006: 520-529

Huang-Liang Chen, Hung-Ming Chen: On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study. SoCC 2006: 203-206

Ming-Ching Lu, Meng-Chen Wu, Hung-Ming Chen, Iris Hui-Ru Jiang: Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design. SoCC 2006: 211-214

Jian-Hung Chen, Hung-Ming Chen, Shinn-Ying Ho: Design of nearest neighbor classifiers: multi-objective approach. Int. J. Approx. Reasoning 40(1-2): 3-22 (2005)

Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong: Simultaneous power supply planning and noise avoidance in floorplan design. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 578-587 (2005)

Bo-Fu Liu, Hung-Ming Chen, Hui-Ling Huang, Shiow-Fen Hwang, Shinn-Ying Ho: Flexible protein-ligand docking using particle swarm optimization. Congress on Evolutionary Computation 2005: 251-258

Shinn-Ying Ho, Chong-Cheng Lee, Hung-Ming Chen, Hui-Ling Huang: Efficient gene selection for classification of microarray data. Congress on Evolutionary Computation 2005: 1753-1760

Bo-Fu Liu, Hung-Ming Chen, Jian-Hung Chen, Shiow-Fen Hwang, Shinn-Ying Ho: MeSwarm: memetic particle swarm optimization. GECCO 2005: 267-268

Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong: Current Calculation on VLSI Signal Interconnects. ISQED 2005: 580-585

Shinn-Ying Ho, Hung-Ming Chen, Shinn-Jang Ho, Tai-Kang Chen: Design of accurate classifiers with a compact fuzzy-rule base using an evolutionary scatter partition of feature space. IEEE Transactions on Systems, Man, and Cybernetics, Part B 34(2): 1031-1044 (2004)

Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang: I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. ICCD 2004: 562-567

Jian-Hung Chen, Hung-Ming Chen, Shinn-Ying Ho: Design of Nearest Neighbor Classifiers Using an Intelligent Multi-objective Evolutionary Algorithm. PRICAI 2004: 262-271

Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong: Floorplanning with power supply noise avoidance. ASP-DAC 2003: 427-430

Li-Da Huang, Hung-Ming Chen, D. F. Wong: Global Wire Bus Configuration with Minimum Delay Uncertainty. DATE 2003: 10050-10055

I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong: Integrated power supply planning and floorplanning. ASP-DAC 2001: 589-594

Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang: Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI 2001: 62-67

Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357