Jia-Wei Chen

Cheng-Yen Chang, Cheng-An Chien, Hsiu-Cheng Chang, Jia-Wei Chen, Jiun-In Guo: A two level mode decision algorithm for H.264 high profile intra encoding. ISCAS 2012: 508-511

Jinn-Shyan Wang, Pei-Yao Chang, Tai-Shin Tang, Jia-Wei Chen, Jiun-In Guo: Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 183-192 (2011)

Jia-Wei Chen, Hsiu-Cheng Chang, Jinn-Shyan Wang, Jiun-In Guo: A dynamic quality-adjustable H.264 intra coder. IEEE Trans. Consumer Electronics 57(3): 1203-1211 (2011)

Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng: A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. ASP-DAC 2011: 73-74

Hsiu-Cheng Chang, Jia-Wei Chen, Bing-Tsung Wu, Ching-Lung Su, Jinn-Shyan Wang, Jiun-In Guo: A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications. IEEE Trans. Circuits Syst. Video Techn. 19(12): 1739-1754 (2009)

Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang: A dynamic quality-scalable H.264 video encoder chip. ASP-DAC 2009: 125-126

Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo: A Dynamic Quality-scalable H.264 Video Encoder. ISCAS 2009: 1932

Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo: A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. SiPS 2007: 521-526

Jia-Wei Chen, Chun-Hao Chang, Chien-Chang Lin, Yi-Huan Yang, Jiun-In Guo, Jinn-Shyan Wang: A Condition-based Intra Prediction Algorithm for H.264/AVC. ICME 2006: 1077-1080

Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo: A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. ISCAS 2006

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen: An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. IEEE Trans. Circuits Syst. Video Techn. 15(5): 704-715 (2005)

Jiun-In Guo, Rei-Chin Ju, Jia-Wei Chen: An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization. IEEE Trans. Circuits Syst. Video Techn. 14(4): 416-428 (2004)

Rei-Chin Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen: A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. ISCAS (2) 2004: 769-772

Jiun-In Guo, Jia-Wei Chen, Han-Chen Chen: A new 2-D 8/spl times/8 DCT/IDT core design using group distributed arithmetic. ISCAS (2) 2003: 752-755