| 2013 | ||
|---|---|---|
| c19 | Xin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya: A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS. ASP-DAC 2013: 109-110 | |
| 2012 | ||
| j10 | Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and VTH-Tuned Oscillator With Fixed Charge Programming. J. Solid-State Circuits 47(5): 1252-1260 (2012) | |
| j9 | Po-Hung Chen, Xin Zhang, Koichi Ishida, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection. J. Solid-State Circuits 47(11): 2554-2562 (2012) | |
| j8 | Xin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya: A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation. IEEE Trans. on Circuits and Systems 59-II(6): 361-365 (2012) | |
| c18 | Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester. ASP-DAC 2012: 469-470 | |
| c17 | Deng-Fa Lin, Po-Hung Chen: Fault Recognition of Wind Turbine Using EMD Analysis and FFT Classification. ICDMA 2012: 414-417 | |
| 2011 | ||
| j7 | Chun-Yao Lee, Po-Hung Chen, Yi-Xing Shen: Maximum power point tracking (MPPT) system of small wind power generator using RBFNN approach. Expert Syst. Appl. 38(10): 12058-12065 (2011) | |
| j6 | Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: 0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications. IEICE Transactions 94-C(4): 598-604 (2011) | |
| j5 | Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai: 0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS. IEICE Transactions 94-C(6): 938-944 (2011) | |
| j4 | Xin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Takayasu Sakurai, Makoto Takamiya: A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage. IEICE Transactions 94-C(6): 953-959 (2011) | |
| c16 | Jyh-Shin Pan, Ming-Yang Chao, E. Yeh, Wen-Wei Yang, Ching-Wen Hsueh, Shyuan Liao, Jian-Bang Lin, Shun-An Yang, Chin-Tai Liu, Tsai-Pao Lee, Jin-Ru Chen, Chia-Hua Chou, Min Chen, Den-Kai Juang, Jen-Hao Yeh, Chieh-Wei Liao, Po-Hung Chen, Kaipon Kao, Chia-Hsin Wu, Wen-Tso Huang, Shih-Hsien Liao, Chih-Heng Shih, Chien-Hsun Tung, Yen-Po Lee: A 70Mb/s -100.5dBm sensitivity 65nm LP MIMO chipset for WiMAX portable router. ISSCC 2011: 136-138 | |
| c15 | Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme. ISSCC 2011: 216-218 | |
| c14 | Lung-Jieh Yang, Chia-Chan Lee, Po-Hung Chen, Chih-Wen Hsu: Confined fractal patterns in gelatin. NEMS 2011: 49-52 | |
| 2010 | ||
| j3 | Po-Hung Chen, Min-Chiao Chen, Chun-Lin Ko, Chung-Yu Wu: An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications. IEICE Transactions 93-C(6): 877-883 (2010) | |
| c13 | Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuaki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: 0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS. CICC 2010: 1-4 | |
| c12 | Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai: 0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS. CICC 2010: 1-4 | |
| c11 | Hung-Cheng Chen, Sin-Yuan Tzeng, Po-Hung Chen: Optimization design of PID controllers for PEMFC with reformer using genetic algorithm. ICMLC 2010: 2990-2995 | |
| c10 | Po-Hung Chen, Hung-Cheng Chen, An Liu, Li-Ming Chen: Pattern recognition for partial discharge diagnosis of power transformer. ICMLC 2010: 2996-3001 | |
| 2007 | ||
| j2 | Ruay Shiung Chang, Po-Hung Chen: Complete and fragmented replica selection and retrieval in Data Grids. Future Generation Comp. Syst. 23(4): 536-546 (2007) | |
| c9 | Po-Hung Chen, Hung-Cheng Chen: Application of Back-Propagation Neural Network to Power Transformer Insulation Diagnosis. ISNN (3) 2007: 26-34 | |
| c8 | Po-Hung Chen: Hydro Plant Dispatch Using Artificial Neural Network and Genetic Algorithm. ISNN (3) 2007: 1120-1129 | |
| 2006 | ||
| j1 | Po-Hung Chen, Hung-Ming Chen, Kuo-Jui Hung, Wen-Hsien Fang, Mon-Chau Shie, Feipei Lai: Markov model fuzzy-reasoning based algorithm for fast block motion estimation. J. Visual Communication and Image Representation 17(1): 131-142 (2006) | |
| c7 | Po-Hung Chen, Hung-Cheng Chen: Application of Evolutionary Neural Network to Power System Unit Commitment. ISNN (2) 2006: 1296-1303 | |
| c6 | Hung-Cheng Chen, Po-Hung Chen, Chien-Ming Chou: 3-D Partial Discharge Patterns Recognition of Power Transformers Using Neural Networks. ISNN (2) 2006: 1324-1331 | |
| 2005 | ||
| c5 | Chun-Liang Hsu, Lawrence Y. Deng, Cheng-Chien Kou, Po-Hung Chen: 3C Intelligent Home Appliance Control System. DMS 2005: 447-449 | |
| c4 | Ruay Shiung Chang, Chih-Min Wang, Po-Hung Chen: Fragmented Replica Selection and Retrieval in Data Grids. GCA 2005: 154-160 | |
| 2004 | ||
| c3 | Ruay Shiung Chang, Chih-Min Wang, Po-Hung Chen: Replica Selection on Co-allocation Data Grids. ISPA 2004: 584-593 | |
| 2001 | ||
| c2 | Po-Hung Chen, Shanq-Jang Ruan, Kuen-Pin Wu, Dai-Xun Hu, Feipei Lai, Kun-Lin Tsai: An entropy-based algorithm to reduce area overhead for bipartition-codec architecture. ISCAS (5) 2001: 49-52 | |
| c1 | Shanq-Jang Ruan, Jen-Chiun Lin, Po-Hung Chen, Kun-Lin Tsai, Feipei Lai: Synthesis of partition-codec architecture for low power and small area circuit design. ISCAS (5) 2001: 523-526 | |
Colors in the list of coauthors
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