Xiaoding Chen

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	2007
j2		Xiaoding Chen, Michael S. Hsiao: An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. IEEE Trans. VLSI Syst. 15(4): 404-412 (2007)
	2006
j1		Xiaoding Chen, Michael S. Hsiao: Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST. IEEE Trans. Computers 55(2): 150-162 (2006)
c3		Xiaoding Chen, Michael S. Hsiao: Characteristic States and Cooperative Game Based Search for Efficient Sequential ATPG and Design Validation. ITC 2006: 1-10
	2003
c2		Xiaoding Chen, Michael S. Hsiao: Energy-Efficient Logic BIST Based on State Correlation Analysis. VTS 2003: 267-272
	2002
c1		Xiaoding Chen, Michael S. Hsiao: Characteristic faults and spectral information for logic BIST. ICCAD 2002: 294-298

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