National University of Defense Technology, Changsha, China
List of publications from the DBLP Bibliography Server - FAQother persons with the same name:
| 2012 | ||
|---|---|---|
| j3 | Wei Chen, Dan Chen, Zhiying Wang: An approach to minimizing the interpretation overhead in Dynamic Binary Translation. The Journal of Supercomputing 61(3): 804-825 (2012) | |
| 2011 | ||
| c17 | Wei Chen, Zhiying Wang, Qiang Dou, Yongwen Wang: A Novel Chaining Approach to Indirect Control Transfer Instructions. ARES 2011: 309-320 | |
| c16 | Xuhao Chen, Wei Chen, Jiawen Li, Zhong Zheng, Li Shen, Zhiying Wang: Characterizing Fine-Grain Parallelism on Modern Multicore Platform. ICPADS 2011: 941-946 | |
| c15 | Wei Chen, Weixia Xu, Zhiying Wang, Qiang Dou, Yongwen Wang, Baokang Zhao, Baosheng Wang: A Formalization of an Emulation Based Co-designed Virtual Machine. IMIS 2011: 164-168 | |
| 2010 | ||
| j2 | Wei Chen, Zhiying Wang, Dan Chen: An Emulator for Executing IA-32 Applications on ARM-Based Systems. JCP 5(7): 1133-1141 (2010) | |
| c14 | Wei Shi, Zhiying Wang, Hongguang Ren, Ting Cao, Wei Chen, Bo Su, Hongyi Lu: DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time. ICCD 2010: 321-327 | |
| c13 | Weixia Xu, Wei Chen, Qiang Dou: A Novel Chaining Approach for Direct Control Transfer Instructions. ICPADS 2010: 664-669 | |
| c12 | Yusong Tan, Wei Chen, Qingbo Wu: Vapor: Virtual Machine Based Parallel Program Profiling Framework. ICPADS 2010: 670-675 | |
| 2009 | ||
| c11 | Wei Chen, Zhiying Wang, Hongyi Lu, Li Shen, Nong Xiao, Zhong Zheng: A Hardware Approach for Reducing Interpretation Overhead. CIT (1) 2009: 98-103 | |
| c10 | Wei Chen, Li Shen, Hongyi Lu, Zhiying Wang, Nong Xiao: A Light-weight Code Cache Design for Dynamic Binary Translation. ICPADS 2009: 120-125 | |
| c9 | Wei Chen, Hongyi Lu, Li Shen, Zhiying Wang, Nong Xiao: Using Pcache to Speedup Interpretation in Dynamic Binary Translation. ISPA 2009: 525-530 | |
| 2008 | ||
| j1 | Rui Gong, Wei Chen, Fang Liu, Kui Dai, Zhiying Wang: A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique. J. Electronic Testing 24(1-3): 57-65 (2008) | |
| c8 | Wei Chen, Hongyi Lu, Li Shen, Zhiying Wang, Nong Xiao: DBTIM: An Advanced Hardware Assisted Full Virtualization Architecture. EUC (2) 2008: 399-404 | |
| c7 | Wei Chen, Hongyi Lu, Li Shen, Zhiying Wang, Nong Xiao, Dan Chen: A Novel Hardware Assisted Full Virtualization Technique. ICYCS 2008: 1292-1297 | |
| c6 | Rui Gong, Wei Chen, Fang Liu, Kui Dai, Zhiying Wang: Control flow checking and recovering based on 8051 architecture. SAC 2008: 1550-1551 | |
| 2006 | ||
| c5 | Wei Chen, Rui Gong, Kui Dai, Fang Liu, Zhiying Wang: Two New Space-Time Triple Modular Redundancy Techniques for Improving Fault Tolerance of Computer Systems. CIT 2006: 175 | |
| c4 | Wei Chen, Rui Gong, Fang Liu, Kui Dai, Zhiying Wang: Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy. ESA 2006: 183-190 | |
| c3 | Rui Gong, Wei Chen, Fang Liu, Kui Dai, Zhiying Wang: Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique. DFT 2006: 184-196 | |
| c2 | Wei Chen, Xuening Wang, Tao Wu, Xin Xu: Visual Protractor Based Localization Algorithm for Mobile Robot. ISDA (3) 2006: 67-71 | |
| c1 | Xuening Wang, Wei Chen, Daxue Liu, Tao Wu, Hangen He: The Optimality Analysis of Hybrid Reinforcement Learning Combined with SVMs. ISDA (1) 2006: 936-941 | |
Colors in the list of coauthors
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