Chung-Kuan Cheng

Xiang Hu, Peng Du, James F. Buckwalter, Chung-Kuan Cheng: Modeling and Analysis of Power Distribution Networks in 3-D ICs. IEEE Trans. VLSI Syst. 21(2): 354-366 (2013)

Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng: Layer minimization in escape routing for staggered-pin-array PCBs. ASP-DAC 2013: 187-192

Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong: A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 31(1): 109-120 (2012)

Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong: Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints". IEEE Trans. on CAD of Integrated Circuits and Systems 31(3): 452 (2012)

Quan Chen, Shih-Hung Weng, Chung-Kuan Cheng: A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 31(7): 1031-1040 (2012)

Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng: Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8): 1180-1193 (2012)

Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald L. Graham: Character design and stamp algorithms for Character Projection Electron-Beam Lithography. ASP-DAC 2012: 725-730

Shih-Hung Weng, Quan Chen, Ngai Wong, Chung-Kuan Cheng: Circuit simulation via matrix exponential method for stiffness handling and parallel processing. ICCAD 2012: 407-414

Quan Chen, Wim Schoenmaker, Shih-Hung Weng, Chung-Kuan Cheng, Guan-Hua Chen, Lijun Jiang, Ngai Wong: A fast time-domain EM-TCAD coupled simulation framework via matrix exponential. ICCAD 2012: 422-428

Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng: Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph. ISPD 2012: 105-112

Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham: Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 167-179 (2011)

Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng: On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals. IEEE Trans. VLSI Syst. 19(3): 520-524 (2011)

Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng: Prediction and Comparison of High-Performance On-Chip Global Interconnection. IEEE Trans. VLSI Syst. 19(7): 1154-1166 (2011)

Zheng Zhang, Xiang Hu, Chung-Kuan Cheng, Ngai Wong: A block-diagonal structured model reduction scheme for power grid networks. DATE 2011: 44-49

Shih-Hung Weng, Peng Du, Chung-Kuan Cheng: A fast and stable explicit integration method by matrix exponential operator for large scale circuit simulation. ISCAS 2011: 1467-1470

Chung-Kuan Cheng: Placement and beyond in honor of Ernest S. Kuh. ISPD 2011: 5-8

Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong: More realistic power grid verification based on hierarchical current and power constraints. ISPD 2011: 159-166

Shan Zeng, Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng: Efficient Power Network Analysis with Modeling of Inductive Effects. IEICE Transactions 93-A(6): 1196-1203 (2010)

Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng: Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness. ACM Trans. Design Autom. Electr. Syst. 15(4) (2010)

Xiang Hu, Thomas Toms, Riko Radojcic, Matt Nowak, Nick Yu, Chung-Kuan Cheng: Enabling power distribution network analysis flows for 3D ICs. 3DIC 2010: 1-4

Wanping Zhang, Ling Zhang, Amirali Shayan Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Ege Engin, Chung-Kuan Cheng: On-chip power network optimization with decoupling capacitors and controlled-ESRs. ASP-DAC 2010: 119-124

Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Arani, Chung-Kuan Cheng: An adaptive parallel flow for power distribution network simulation using discrete Fourier transform. ASP-DAC 2010: 125-130

Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng: Bus via reduction based on floorplan revising. ACM Great Lakes Symposium on VLSI 2010: 9-14

Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng: Physical synthesis of bus matrix for high bandwidth low power on-chip communications. ISPD 2010: 91-96

Peng Du, Xiang Hu, Shih-Hung Weng, Amirali Shayan Arani, Xiaoming Chen, A. Ege Engin, Chung-Kuan Cheng: Worst-case noise prediction with non-zero current transition times for early power distribution system verification. ISQED 2010: 624-631

Yulei Zhang, James F. Buckwalter, Chung-Kuan Cheng: Performance prediction of throughput-centric pipelined global interconnects with voltage scaling. SLIP 2010: 69-76

Chung-Kuan Cheng, Andrew B. Kahng, Kambiz Samadi, Amirali Shayan Arani: Worst-case performance prediction under supply voltage and temperature variation. SLIP 2010: 91-96

Wenjian Yu, Rui Shi, Chung-Kuan Cheng: Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design. IEICE Transactions 92-C(4): 444-452 (2009)

Shan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng: Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures. IEICE Transactions 92-A(6): 1476-1484 (2009)

Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng: Efficient Power Network Analysis Considering Multidomain Clock Gating. IEEE Trans. on CAD of Integrated Circuits and Systems 28(9): 1348-1358 (2009)

Yi Zhu, Thomas Weng, Chung-Kuan Cheng: Enhancing Learning Effectiveness in Digital Design Courses Through the Use of Programmable Logic Boards. IEEE Trans. Education 52(1): 151-156 (2009)

Yi Zhu, Yuanfang Hu, Michael Bedford Taylor, Chung-Kuan Cheng: Energy and switch area optimizations for FPGA global routing architectures. ACM Trans. Design Autom. Electr. Syst. 14(1) (2009)

Chung-Kuan Cheng: Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders. IEEE Symposium on Computer Arithmetic 2009: 212

Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng: High performance on-chip differential signaling using passive compensation for global communication. ASP-DAC 2009: 385-390

Wanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan Arani, Renshen Wang, Zhi Zhu, Chung-Kuan Cheng: Noise minimization during power-up stage for a multi-domain power network. ASP-DAC 2009: 391-396

He Peng, Chung-Kuan Cheng: Parallel transistor level circuit simulation using domain decomposition methods. ASP-DAC 2009: 397-402

Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng: Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. DAC 2009: 166-171

Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kuan Cheng, Wenjian Yu, Mikhail Popovich, Thomas Toms, Xiaoming Chen: Reliability aware through silicon via planning for 3D stacked ICs. DATE 2009: 288-291

He Peng, Chung-Kuan Cheng: Parallel transistor level full-chip circuit simulation. DATE 2009: 304-307

Renshen Wang, Chung-Kuan Cheng: Octilinear redistributive routing in bump arrays. ACM Great Lakes Symposium on VLSI 2009: 191-196

Renshen Wang, Chung-Kuan Cheng: On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design. ACM Great Lakes Symposium on VLSI 2009: 257-262

Renshen Wang, Takumi Okamoto, Chung-Kuan Cheng: Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations. ICCD 2009: 23-28

Amirali Shayan Arani, Xiang Hu, Wanping Zhang, Chung-Kuan Cheng, A. Ege Engin, Xiaoming Chen, Mikhail Popovich: 3D stacked power distribution considering substrate coupling. ICCD 2009: 225-230

Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng: Design methodology of high performance on-chip global interconnect using terminated transmission-line. ISQED 2009: 451-458

Amirali Shayan Arani, Xiang Hu, He Peng, Wenjian Yu, Wanping Zhang, Chung-Kuan Cheng, Mikhail Popovich, Xiaoming Chen, Lew Chua-Eoan, Xiaohua Kong: Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network. ISQED 2009: 576-581

Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng: Efficient power network analysis with complete inductive modeling. ISQED 2009: 770-775

Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng: Prediction of high-performance on-chip global interconnection. SLIP 2009: 61-68

Xiang Hu, Wenbo Zhao, Peng Du, Yulei Zhang, Amirali Shayan Arani, Christopher Pan, A. Ege Engin, Chung-Kuan Cheng: On the bound of time-domain power supply noise based on frequency-domain target impedance. SLIP 2009: 69-76

Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng: Predicting the worst-case voltage violation in a 3D power network. SLIP 2009: 93-98

Chung-Kuan Cheng, Sherief Reda (Eds.): The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings. ACM 2009, isbn 978-1-60558-576-5

Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng: Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration. IEICE Transactions 91-A(12): 3474-3480 (2008)

Yi Zhu, Amirali Shayan Arani, Wanping Zhang, Tong Lee Chen, Tzyy-Ping Jung, Jeng-Ren Duann, Scott Makeig, Chung-Kuan Cheng: Analyzing High-Density ECG Signals Using ICA. IEEE Trans. Biomed. Engineering 55(11): 2528-2537 (2008)

Yi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng: Timing-power optimization for mixed-radix Ling adders by integer linear programming. ASP-DAC 2008: 131-137

Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto: High performance current-mode differential logic. ASP-DAC 2008: 720-725

Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng: Low power passive equalizer optimization using tritonic step response. DAC 2008: 570-573

Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng: Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. DATE 2008: 537-540

Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng: Low Power Passive Equalizer Design for Computer Memory Links. Hot Interconnects 2008: 51-56

Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng: A novel fixed-outline floorplanner with zero deadspace for hierarchical design. ICCAD 2008: 16-23

Yi Zhu, Michael Bedford Taylor, Scott B. Baden, Chung-Kuan Cheng: Advancing supercomputer performance through interconnection topology synthesis. ICCAD 2008: 555-558

Rui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, Ernest S. Kuh: Efficient and accurate eye diagram prediction for high speed signaling. ICCAD 2008: 655-661

Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng: On-chip high performance signaling using passive compensation. ICCD 2008: 182-187

Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng: 3-D floorplanning using labeled tree and dual sequences. ISPD 2008: 54-59

Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng: Clock Skew Analysis via Vector Fitting in Frequency Domain. ISQED 2008: 476-479

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 645-658 (2007)

Zhengyong Zhu, He Peng, Chung-Kuan Cheng, Khosro Rouz, Manjit Borah, Ernest S. Kuh: Two-Stage Newton-Raphson Method for Transistor-Level Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 881-895 (2007)

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng: Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 959-969 (2007)

Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis: Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. ASP-DAC 2007: 609-615

Haikun Zhu, Yi Zhu, Chung-Kuan Cheng, David M. Harris: An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization. ASP-DAC 2007: 616-621

Haikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen: Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. ASP-DAC 2007: 684-689

Amirali Shayan Arani, Yi Zhu, Yi-Ning Cheng, Chung-Kuan Cheng, Shien-Fong Lin, Peng-Sheng Chen: Exploring Cardioneural Signals from Noninvasive ECG Measurement. BIBE 2007: 1134-1138

Yuanfang Hu, Yi Zhu, Michael Bedford Taylor, Chung-Kuan Cheng: FPGA global routing architecture optimization using a multicommodity flow approach. ICCD 2007: 144-151

Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng: Fast power network analysis with multiple clock domains. ICCD 2007: 456-463

Chun-Chen Liu, Haikun Zhu, Chung-Kuan Cheng: Passive compensation for high performance inter-chip communication. ICCD 2007: 547-552

Wanping Zhang, Chung-Kuan Cheng: Incremental Power Impedance Optimization Using Vector Fitting Modeling. ISCAS 2007: 2439-2442

He Peng, Chung-Kuan Cheng: Fast Transient Simulation of Lossy Transmission Lines. ISCAS 2007: 2706-2709

Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng: Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. ISQED 2007: 251-256

Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu: General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21(6): 922-926 (2006)

Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham: On the construction of zero-deficiency parallel prefix circuits with minimum depth. ACM Trans. Design Autom. Electr. Syst. 11(2): 387-409 (2006)

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton: Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. ASP-DAC 2006: 73-78

Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh: An unconditional stable general operator splitting method for transistor level transient analysis. ASP-DAC 2006: 428-433

Yi Zhu, Tong Lee Chen, Wanping Zhang, Tzyy-Ping Jung, Jeng-Ren Duann, Scott Makeig, Chung-Kuan Cheng: Noninvasive Study of the Human Heart using Independent Component Analysis. BIBE 2006: 340-347

Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng: Communication latency aware low power NoC synthesis. DAC 2006: 574-579

Rui Shi, Chung-Kuan Cheng: Efficient escape routing for hexagonal array of high density I/Os. DAC 2006: 1003-1008

Jianhua Liu, Michael Chang, Chung-Kuan Cheng: An iterative division algorithm for FPGAs. FPGA 2006: 83-89

Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng: Timing model reduction for hierarchical timing analysis. ICCAD 2006: 415-422

Renshen Wang, Rui Shi, Chung-Kuan Cheng: Layer minimization of escape routing in area array packaging. ICCAD 2006: 815-819

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185

Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao: The Y architecture for on-chip interconnect: analysis and methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 588-599 (2005)

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu: Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 609-621 (2005)

Hongyu Chen, Chung-Kuan Cheng: A multi-level transmission line network approach for multi-giga hertz clock distribution. ASP-DAC 2005: 103-106

Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen: Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC 2005

Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh: Efficient transient simulation for transistor-level analysis. ASP-DAC 2005: 240-243

Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham: Constructing zero-deficiency parallel prefix adder of minimum depth. ASP-DAC 2005: 883-888

Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng: Integrated algorithmic logical and physical design of integer multiplier. ASP-DAC 2005: 1014-1017

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris: Improving the efficiency of static timing analysis with false paths. ICCAD 2005: 527-531

Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng: Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz. ICCD 2005: 111-118

Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris: Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications. ICCD 2005: 497-502

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng: Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng: VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225

Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris: Unified quadratic programming approach for mixed mode placement. ISPD 2005: 193-199

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng: Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng: Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633

Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Corner block list representation and its application with boundary constraints. Science in China Series F: Information Sciences 47(1): 1-19 (2004)

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: A buffer planning algorithm for chip-level floorplanning. Science in China Series F: Information Sciences 47(6): 763-776 (2004)

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu: Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004)

Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen: Fast postplacement optimization using functional symmetries. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 102-118 (2004)

Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu: UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 358-365 (2004)

Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai: Area minimization of power distribution network using efficient nonlinear programming techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1086-1094 (2004)

Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004)

Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng: A multiple level network approach for clock skew minimization with process variations. ASP-DAC 2004: 263-268

Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang: Optimal planning for mesh-based power distribution. ASP-DAC 2004: 444-449

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623

Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris: Fast adders in modern FPGAs. FPGA 2004: 250

Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham: Floorplan representations: Complexity and connections. ACM Trans. Design Autom. Electr. Syst. 8(1): 55-80 (2003)

Zhanhai Qin, Chung-Kuan Cheng: RCLK-VJ network reduction with Hurwitz polynomial approximation. ASP-DAC 2003: 283-291

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: A buffer planning algorithm based on dead space redistribution. ASP-DAC 2003: 435-438

Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu: UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. ASP-DAC 2003: 834-839

Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng: The Y-architecture: yet another on-chip interconnect solution. ASP-DAC 2003: 840-847

Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng: Power network analysis using an adaptive algebraic multigrid approach. DAC 2003: 105-108

Zhanhai Qin, Chung-Kuan Cheng: Realizable parasitic reduction using generalized Y-Delta transformation. DAC 2003: 220-225

Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu: An algebraic multigrid solver for analytical placement with layout based clustering. DAC 2003: 794-799

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811

Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao: The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. ICCAD 2003: 13-20

Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng: An Algorithmic Approach for Generic Parallel Adders. ICCAD 2003: 734-740

Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu: Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142

Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang: Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. SLIP 2003: 71-76

Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham: A hierarchical three-way interconnect architecture for hexagonal processors. SLIP 2003: 133-139

Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai: An Optimum Placement Search Algorithm Based on Extended Corner Block List. J. Comput. Sci. Technol. 17(6): 699-707 (2002)

Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt: Toward better wireload models in the presence of obstacles. IEEE Trans. VLSI Syst. 10(2): 177-189 (2002)

Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng: Physical Planning Of On-Chip Interconnect Architectures. ICCD 2002: 30-35

Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham: Balancing the Interconnect Topology for Arrays of Processors between Cost and Power. ICCD 2002: 180-186

Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng: Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. SLIP 2002: 85-89

Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. VLSI Design 2002: 387-392

Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Floorplanning with abutment constraints based on corner block list. Integration 31(1): 65-77 (2001)

Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, Takeshi Yoshimura: Floorplanning using a tree representation. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 281-289 (2001)

Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu: VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC 2001: 509-514

Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt: Toward better wireload models in the presence of obstacles. ASP-DAC 2001: 527-532

Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC 2001: 770-775

Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai: Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. ICCAD 2001: 153-157

Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham: Revisiting floorplan representations. ISPD 2001: 138-143

Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu: ECBL: an extended corner block list with solution space including optimum placement. ISPD 2001: 150-155

Yingxin Pang, Chung-Kuan Cheng, Koen Lampaert, Weize Xie: Rectilinear block packing using O-tree representation. ISPD 2001: 156-161

Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu: Interconnect implications of growth-based structural models for VLSI circuits. SLIP 2001: 99-106

Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng: A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation. ASP-DAC 2000: 463-468

Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska: Fast post-placement rewiring using easily detectable functional symmetries. DAC 2000: 286-289

Yingxin Pang, Florin Balasa, Koen Lampaert, Chung-Kuan Cheng: Block placement with symmetry constraints based on the O-tree non-slicing representation. DAC 2000: 464-467

Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu: Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD 2000: 8-12

Xiaodong Yang, Chung-Kuan Cheng, Walter H. Ku, Robert J. Carragher: Hurwitz Stable Reduced Order Modelling for RLC Interconnect Trees. ICCAD 2000: 222-228

Yingxin Pang, Chung-Kuan Cheng, Takeshi Yoshimura: An enhanced perturbing algorithm for floorplan design using the O-tree representation. ISPD 2000: 168-173

John Lillis, Chung-Kuan Cheng: Timing optimization for multisource nets: characterization andoptimal repeater insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 322-331 (1999)

Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng: Sequence-pair approach for rectilinear module placement. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 484-493 (1999)

Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen: A Performance-Driven I/O Pin Routing Algorithm. ASP-DAC 1999: 129-132

Pei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura: An O-Tree Representation of Non-Slicing Floorplan and Its Applications. DAC 1999: 268-273

Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng: RLC interconnect delay estimation via moments of amplitude and phase response. ICCAD 1999: 208-213

Jianmin Li, Chung-Kuan Cheng: Routability improvement using dynamic interconnect architecture. IEEE Trans. VLSI Syst. 6(3): 498-501 (1998)

Fang-Jou Liu, Chung-Kuan Cheng: Extending Moment Computation to 2-Port Circuit Representations. DAC 1998: 473-476

Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng: Rectilinear block placement using sequence-pair. ISPD 1998: 173-178

Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh: TIGER: an efficient timing-driven global router for gate array and standard cell layout design. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1323-1331 (1997)

Fang-Jou Liu, John Lillis, Chung-Kuan Cheng: A new layout-driven timing model for incremental layout optimization. ASP-DAC 1997: 127-131

Jonathan Dufour, Robert McBride, Ping Zhang, Chung-Kuan Cheng: A building block placement tool. ASP-DAC 1997: 271-276

John Lillis, Chung-Kuan Cheng: Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. DAC 1997: 214-219

Ming-Ter Kuo, Chung-Kuan Cheng: A Network Flow Approach for Hierarchical Tree Partitioning. DAC 1997: 512-517

Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng: Cluster Refinement for Block Placement. DAC 1997: 762-765

Robert C. Carden IV, Jianmin Li, Chung-Kuan Cheng: A global router with a theoretical bound on the optimal solution. IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 208-216 (1996)

Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng: Performance driven bus buffer insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 429-437 (1996)

Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi: Solving the net matching problem in high-performance chip design. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 902-911 (1996)

Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau: A wire length estimation technique utilizing neighborhood density equations. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 912-922 (1996)

Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng: New Spectral Linear Placement and Clustering Approach. DAC 1996: 88-93

Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng: Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming. DAC 1996: 274-279

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho: New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. DAC 1996: 395-400

Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng: Network Partitioning into Tree Hierarchies. DAC 1996: 477-482

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin: Simultaneous Routing and Buffer Insertion for High Performance Interconnect. Great Lakes Symposium on VLSI 1996: 148-153

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: Optimization by iterative improvement: an experimental evaluation on two-way partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 145-153 (1995)

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: Circuit clustering using a stochastic flow injection method. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 154-162 (1995)

So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo: A cell-based hierarchical pitchmatching compaction using minimal LP. IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 523-526 (1995)

Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu: A replication cut for two-way partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 623-630 (1995)

Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof: Local ratio cut and set covering partitioning for huge logic emulation systems. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1085-1092 (1995)

Jiao Fan, D. Zaleta, Chung-Kuan Cheng, S. H. Lee: Physical models and algorithms for optoelectronic MCM layout. IEEE Trans. VLSI Syst. 3(1): 124-135 (1995)

Nan-Chi Chou, Chung-Kuan Cheng: On general zero-skew clock net construction. IEEE Trans. VLSI Syst. 3(1): 141-146 (1995)

Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin: Performance driven multiple-source bus synthesis using buffer insertion. ASP-DAC 1995

Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu: Performance-Driven Partitioning Using a Replication Graph Approach. DAC 1995: 206-210

Jianmin Li, Chung-Kuan Cheng: Routability improvement using dynamic interconnect architecture. FCCM 1995: 61-67

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin: Optimal wire sizing and buffer insertion for low power and a generalized delay model. ICCAD 1995: 138-143

Jianmin Li, John Lillis, Chung-Kuan Cheng: Linear decomposition algorithm for VLSI design applications. ICCAD 1995: 223-228

Lung-Tien Liu, Ming-Ter Kuo, Shih-Chen Huang, Chung-Kuan Cheng: A gradient method on the initial partition of Fiduccia-Mattheyses algorithm. ICCAD 1995: 229-234

Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng: Simple tree-construction heuristics for the fanout problem . ICCD 1995: 671-679

Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng: Finite State Machine Decomposition for I/O Minimization. ISCAS 1995: 1061-1064

Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin: Optimization of power dissipation and skew sensitivity in clock buffer synthesis. ISLPD 1995: 179-184

So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu: A multi-probe approach for MCM substrate testing. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 110-121 (1994)

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: A general purpose, multiple-way partitioning algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1480-1488 (1994)

Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel: Block-oriented programmable design with switching network interconnect. IEEE Trans. VLSI Syst. 2(1): 45-53 (1994)

Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof: Circuit Partitioning for Huge Logic Emulation Systems. DAC 1994: 244-249

Lung-Tien Liu, Minshine Shih, Chung-Kuan Cheng: Data Flow Partitioning for Clock Period and Latency Minimization. DAC 1994: 658-663

Jae Chung, Chung-Kuan Cheng: Skew sensitivity minimization of buffered clock tree. ICCAD 1994: 280-283

Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang: Performance-Driven Steiner Tree Algorithm for Global Routing. DAC 1993: 177-181

So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo: Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. DAC 1993: 395-400

Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau: Prime: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach. DAC 1993: 531-536

Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh: An Efficient Timing-Driven Global Routing Algorithm. DAC 1993: 596-600

Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku: Performance-driven partitioning using retiming and replication. ICCAD 1993: 296-299

Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita: An efficient algorithm for the net matching problem. ICCAD 1993: 640-644

Chung-Kuan Cheng, T. C. Hu: Maximum Concurrent Flows and Minimum Cuts. Algorithmica 8(3): 233-249 (1992)

Chung-Kuan Cheng: The optimal partitioning of networks. Networks 22(3): 297-315 (1992)

Chung-Kuan Cheng, David N. Deutsch, Craig Shohara, Mark Taparauskas, Mark Bubien: Geometric compaction on channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 115-127 (1992)

Chung-Kuan Cheng, Ximtie Deng, Yuh-Zen Liao, So-Zen Yao: Symbolic layout compaction under conditional design rules. IEEE Trans. on CAD of Integrated Circuits and Systems 11(4): 475-486 (1992)

Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau: A Wire Length Estimation Technique Utilizing Neighborhood Density Equations. DAC 1992: 57-61

Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh: FARM: An Efficient Feed-Through Pin Assignment Algorithm. DAC 1992: 530-535

So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu: An optimal probe testing algorithm for the connectivity verification of MCM substrates. ICCAD 1992: 264-267

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: A probabilistic multicommodity-flow solution to circuit clustering problems. ICCAD 1992: 428-431

Chung-Kuan Cheng, So-Zen Yao, T. C. Hu: The Orientation of Modules Based on Graph Decomposition. IEEE Trans. Computers 40(6): 774-780 (1991)

Yen-Chuen A. Wei, Chung-Kuan Cheng: Ratio cut partitioning for hierarchical designs. IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 911-921 (1991)

Chung-Kuan Cheng, Yen-Chuen A. Wei: An improved two-way partitioning algorithm with stable performance [VLSI]. IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1502-1511 (1991)

Robert C. Carden IV, Chung-Kuan Cheng: A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm. DAC 1991: 316-321

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: A General Purpose Multiple Way Partitioning Algorithm. DAC 1991: 421-426

Yen-Chuen A. Wei, Chung-Kuan Cheng: A Two-Level Two-Way Partitioning Algorithm. ICCAD 1990: 516-519

Chung-Kuan Cheng, T. C. Hu: Ancestor Tree for Arbitrary Multi-Terminal Cut Functions. IPCO 1990: 115-127

Chung-Kuan Cheng, David N. Deutsch: Improved Channel Routing by Via Minimization and Shifting. DAC 1988: 677-680

Chung-Kuan Cheng: Linear placement algorithms and applications to VLSI design. Networks 17(4): 439-464 (1987)

Chung-Kuan Cheng, Ernest S. Kuh: Module Placement Based on Resistive Network Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 218-225 (1984)