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Kwang-Ting Cheng
Kwang-Ting (Tim) Cheng
2010 – today
- 2013
[j86]Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng, Cheng-Wen Wu: Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. IEEE Trans. VLSI Syst. 21(3): 465-474 (2013)- [c236]Peter Lisherness, Nicole Lesperance, Kwang-Ting (Tim) Cheng: Mutation analysis with coverage discounting. DATE 2013: 31-34
- 2012
- [c235]Alex A. T. Bui, Kwang-Ting Cheng, Jason Cong, Luminita A. Vese, Yi-Chu Wang, Bo Yuan, Yi Zou: Platform characterization for Domain-Specific Computing. ASP-DAC 2012: 94-99
- [c234]Peter Lisherness, Kwang-Ting Cheng: Improving validation coverage metrics to account for limited observability. ASP-DAC 2012: 292-297
- [c233]Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amirali Ghofrani, Shiyuan Yang, Kwang-Ting Cheng: Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems. ASP-DAC 2012: 615-620
- [c232]Ming Gao, Peter Lisherness, Kwang-Ting Cheng, Jing-Jia Liou: On error modeling of electrical bugs for post-silicon timing validation. ASP-DAC 2012: 701-706
- [c231]Yan Zheng, Peter Lisherness, Ming Gao, Jock Bovington, Shiyuan Yang, Kwang-Ting Cheng: Power-efficient calibration and reconfiguration for on-chip optical communication. DATE 2012: 1501-1506
- [c230]Xin Yang, Kwang-Ting Cheng: LDB: An ultra-fast feature for scalable Augmented Reality on mobile devices. ISMAR 2012: 49-57
- [c229]Ming Gao, Peter Lisherness, Kwang-Ting (Tim) Cheng: Adaptive test selection for post-silicon timing validation: A data mining approach. ITC 2012: 1-7
- [c228]Xin Yang, Kwang-Ting (Tim) Cheng: Accelerating SURF detector on mobile devices. ACM Multimedia 2012: 569-578
- [c227]Yi-Chu Wang, Kwang-Ting (Tim) Cheng: Energy and Performance Characterization of Mobile Heterogeneous Computing. SiPS 2012: 312-317
- [c226]Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, Valeria Bertacco: Comprehensive online defect diagnosis in on-chip networks. VTS 2012: 44-49
- 2011
- [j85]Jiun-Lang Huang, Kwang-Ting (Tim) Cheng: A Promising Alternative to Conventional Silicon. IEEE Design & Test of Computers 28(6): 6 (2011)
- [j84]Tsung-Ching Huang, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng: Robust Circuit Design for Flexible Electronics. IEEE Design & Test of Computers 28(6): 8-15 (2011)
- [j83]Saeed Shamshiri, Kwang-Ting (Tim) Cheng: Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip. IEEE Trans. Computers 60(9): 1246-1259 (2011)
- [j82]Ming Gao, Hsiu-Ming Chang, Peter Lisherness, Kwang-Ting (Tim) Cheng: Time-Multiplexed Online Checking. IEEE Trans. Computers 60(9): 1300-1312 (2011)
- [j81]Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Cheng: Tester-Assisted Calibration and Screening for Digitally-Calibrated ADCs. IEEE Trans. on Circuits and Systems 58-I(12): 2838-2848 (2011)
- [j80]Mei-Chen Yeh, Kwang-Ting Cheng: Fast Visual Retrieval Using Accelerated Sequence Matching. IEEE Transactions on Multimedia 13(2): 320-329 (2011)
- [c225]Ming Gao, Peter Lisherness, Kwang-Ting (Tim) Cheng: Post-silicon bug detection for variation induced electrical bugs. ASP-DAC 2011: 273-278
- [c224]Hsiu-Ming Chang, Kwang-Ting (Tim) Cheng: Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers. DAC 2011: 759-764
- [c223]Ping-Ying Wang, Hsiu-Ming Chang, Kwang-Ting Cheng: An all-digital built-in self-test technique for transfer function characterization of RF PLLs. DATE 2011: 359-364
- [c222]Peter Lisherness, Kwang-Ting (Tim) Cheng: Coverage discounting: A generalized approach for testbench qualification. HLDVT 2011: 49-56
- [c221]Hsiu-Ming Chang, Kwang-Ting Cheng, Wangyang Zhang, Xin Li, Kenneth M. Butler: Test cost reduction through performance prediction using virtual probe. ITC 2011: 1-9
- [c220]Saeed Shamshiri, Amirali Ghofrani, Kwang-Ting Cheng: End-to-end error correction and online diagnosis for on-chip networks. ITC 2011: 1-10
- [c219]Xin Yang, Qiong Liu, Chunyuan Liao, Kwang-Ting Cheng, Andreas Girgensohn: Large-scale EMM identification based on geometry-constrained visual word correspondence voting. ICMR 2011: 35
- [c218]Xin Yang, Chunyuan Liao, Qiong Liu, Kwang-Ting Cheng: Minimum correspondence sets for improving large-scale augmented paper. VRCAI 2011: 59-68
- 2010
- [b1]Dongwoo Hong, Kwang-Ting Cheng: Efficient Test Methodologies for High-Speed Serial Links. Lecture Notes in Electrical Engineering 51, Springer 2010, ISBN 978-90-481-3442-7, pp. 1-90
- [j79]Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Cheng: Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study. J. Electronic Testing 26(1): 59-71 (2010)
- [c217]Peter Lisherness, Kwang-Ting (Tim) Cheng: SCEMIT: a systemc error and mutation injection tool. DAC 2010: 228-233
- [c216]Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu: An error tolerance scheme for 3D CMOS imagers. DAC 2010: 917-922
- [c215]Tsung-Ching Huang, Kenjiro Fukuda, Chun-Ming Lo, Yung-Hui Yeh, Tsuyoshi Sekitani, Takao Someya, Kwang-Ting Cheng: Pseudo-CMOS: A novel design style for flexible electronics. DATE 2010: 154-159
- [c214]Chun-Ming Lo, Tsung-Ching Huang, Cheng-Yi Chiang, J. Hou, Kwang-Ting Cheng: A portable multi-pitch e-drum based on printed flexible pressure sensors. DATE 2010: 1082-1087
- [c213]Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada: An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. DATE 2010: 1755-1760
- [c212]Yi-Chu Wang, Bryan Donyanavard, Kwang-Ting (Tim) Cheng: Energy-Aware Real-Time Face Recognition System on Mobile CPU-GPU Platform. ECCV Workshops (1) 2010: 411-422
- [c211]Ming Gao, Kwang-Ting Cheng: A case study of Time-Multiplexed Assertion Checking for post-silicon debugging. HLDVT 2010: 90-96
- [c210]Saeed Shamshiri, Kwang-Ting Cheng: Error-locality-aware linear coding to correct multi-bit upsets in SRAMs. ITC 2010: 202-211
- [c209]Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li: nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. ITC 2010: 343-352
- [c208]Shujun Deng, Kwang-Ting Cheng, Jinian Bian, Zhiqiu Kong: Mutation-based diagnostic test generation for hardware design error diagnosis. ITC 2010: 815
- [c207]Yi-Chu Wang, Sydney Pang, Kwang-Ting Cheng: A GPU-accelerated face annotation system for smartphones. ACM Multimedia 2010: 1667-1668
- [c206]Kwang-Ting Cheng: Innovative practices session 2C: Design, fabrication and test of flexible electronics. VTS 2010: 81
- [c205]Kwang-Ting Cheng, Tsung-Ching Huang: Design, analysis, and test of low-power and reliable flexible electronics. VTS 2010: 82
- [c204]Saeed Shamshiri, Kwang-Ting Cheng: Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy. VTS 2010: 194-199
- [c203]Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting Cheng: Calibration-assisted production testing for digitally-calibrated ADCs. VTS 2010: 295-300
2000 – 2009
- 2009
- [j78]Feng Lu, Kwang-Ting Cheng: SEChecker: A Sequential Equivalence Checking Framework Based on Kth Invariants. IEEE Trans. VLSI Syst. 17(6): 733-746 (2009)
- [c202]Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting Cheng: Calibration as a Functional Test: An ADC Case Study. Asian Test Symposium 2009: 85-86
- [c201]Ming Gao, Kwang-Ting Cheng: Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder. Asian Test Symposium 2009: 119-124
- [c200]
- [c199]
- [c198]Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada: Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links. European Test Symposium 2009: 107-112
- [c197]Peter Lisherness, Kwang-Ting Cheng: An instrumented observability coverage method for system validation. HLDVT 2009: 88-93
- [c196]Hsiu-Ming Chang, Kuan-Yu Lin, Chin-Hsuan Chen, Kwang-Ting Cheng: A Built-in self-calibration scheme for pipelined ADCs. ISQED 2009: 266-271
- [c195]Mei-Chen Yeh, Kwang-Ting Cheng: A compact, effective descriptor for video copy detection. ACM Multimedia 2009: 633-636
- [c194]Xin Yang, Qiang Zhu, Kwang-Ting Cheng: MyFinder: near-duplicate detection for large image collections. ACM Multimedia 2009: 1013-1014
- [c193]
- [c192]Dong Xiang, Boxue Yin, Kwang-Ting Cheng: Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure. VTS 2009: 251-256
- [c191]Hsiu-Ming Chang, Chin-Hsuan Chen, Kuan-Yu Lin, Kwang-Ting Cheng: Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC. VTS 2009: 291-296
- 2008
- [j77]
- [j76]Kwang-Ting (Tim) Cheng: Test compression saves bits, cycles, and money. IEEE Design & Test of Computers 25(2): 105 (2008)
- [j75]Kwang-Ting (Tim) Cheng: Effective silicon debug is key for time to money. IEEE Design & Test of Computers 25(3): 204 (2008)
- [j74]Kwang-Ting (Tim) Cheng: Not just research as usual. IEEE Design & Test of Computers 25(4): 292 (2008)
- [j73]Kwang-Ting (Tim) Cheng: Design and test for reliability and efficiency. IEEE Design & Test of Computers 25(6): 508 (2008)
- [j72]Tsung-Ching Huang, Kwang-Ting (Tim) Cheng, Huai-Yuan Tseng, Chen-Pang Kung: Reliability analysis for flexible electronics: Case study of integrated a-Si: H TFT scan driver. JETC 4(3) (2008)
- [j71]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang: A Clock-Less Jitter Spectral Analysis Technique. IEEE Trans. on Circuits and Systems 55-I(8): 2263-2272 (2008)
- [c190]Saeed Mirzaeian, Feijun (Frank) Zheng, Kwang-Ting (Tim) Cheng: RTL Error Diagnosis Using a Word-Level SAT-Solver. ITC 2008: 1-8
- [c189]Saeed Shamshiri, Peter Lisherness, Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng: A Cost Analysis Framework for Multi-core Systems with Spares. ITC 2008: 1-8
- [c188]Mei-Chen Yeh, Kwang-Ting Cheng: A string matching approach for visual retrieval and classification. Multimedia Information Retrieval 2008: 52-58
- [c187]Shih-Wei Chu, Mei-Chen Yeh, Kwang-Ting Cheng: A real-time, embedded face-annotation system. ACM Multimedia 2008: 989-990
- [c186]Dongwoo Hong, Kwang-Ting (Tim) Cheng: Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links. VTS 2008: 17-22
- [p1]Laung-Terng Wang, Charles E. Stroud, Kwang-Ting (Tim) Cheng: Logic Testing. Wiley Encyclopedia of Computer Science and Engineering 2008
- 2007
- [j70]Kwang-Ting (Tim) Cheng: Moore's law meets the life sciences. IEEE Design & Test of Computers 24(1): 4 (2007)
- [j69]Kwang-Ting (Tim) Cheng: Cocktail approach to functional verification. IEEE Design & Test of Computers 24(2): 108 (2007)
- [j68]Kwang-Ting (Tim) Cheng: Supporting cost-effective innovation. IEEE Design & Test of Computers 24(3): 212 (2007)
- [j67]Kwang-Ting (Tim) Cheng: Design and CAD for Nanotechnologies. IEEE Design & Test of Computers 24(4): 300 (2007)
- [j66]Kwang-Ting (Tim) Cheng: Combining synchronous and asynchronous timing schemes for high-performance systems. IEEE Design & Test of Computers 24(5): 412 (2007)
- [j65]Kwang-Ting (Tim) Cheng: Trustworthy ICs for secure embedded computing. IEEE Design & Test of Computers 24(6): 516 (2007)
- [j64]Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng: Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 932-942 (2007)
- [j63]Kai Yang, Kwang-Ting Cheng: Silicon Debug for Timing Errors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2084-2088 (2007)
- [c185]Tsung-Ching Huang, Huai-Yuan Tseng, Chen-Pang Kung, Kwang-Ting Cheng: Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si: H TFT Scan Driver. DAC 2007: 966-969
- [c184]Mitchell Lin, Kwang-Ting (Tim) Cheng: Testable design for advanced serial-link transceivers. DATE 2007: 695-700
- [c183]Dongwoo Hong, Shadi Saberi, Kwang-Ting Cheng, C. Patrick Yue: A two-tone test method for continuous-time adaptive equalizers. DATE 2007: 1283-1288
- [c182]Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng: A framework for system reliability analysis considering both system error tolerance and component test quality. DATE 2007: 1581-1586
- [c181]Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei: A hybrid scheme for compacting test responses with unknown values. ICCAD 2007: 513-519
- [c180]Jin-Fu Li, Feijun (Frank) Zheng, Kwang-Ting Cheng: Diagnosing scan chains using SAT-based diagnostic pattern generation. SoCC 2007: 273-276
- 2006
- [j62]Kwang-Ting Cheng: New beginnings, continued success. IEEE Design & Test of Computers 23(1): 5-6 (2006)
- [j61]Kwang-Ting (Tim) Cheng: Dealing with early life failures. IEEE Design & Test of Computers 23(2): 85 (2006)
- [j60]Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng: Test Consideration for Nanometer-Scale CMOS Circuits. IEEE Design & Test of Computers 23(2): 128-136 (2006)
- [j59]Kwang-Ting (Tim) Cheng: The Need for a SiP Design and Test Infrastructure. IEEE Design & Test of Computers 23(3): 181 (2006)
- [j58]
- [j57]Kwang-Ting (Tim) Cheng: The New World of ESL Design. IEEE Design & Test of Computers 23(5): 333 (2006)
- [j56]Kwang-Ting (Tim) Cheng: Handling variations and uncertainties. IEEE Design & Test of Computers 23(6): 434 (2006)
- [j55]Salvador Mir, Kwang-Ting (Tim) Cheng, Andrew Richardson: Guest Editorial. J. Electronic Testing 22(4-6): 311 (2006)
- [j54]Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng: Simulation-Based Functional Test Generation for Embedded Processors. IEEE Trans. Computers 55(11): 1335-1343 (2006)
- [j53]Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng: Pseudofunctional testing. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1535-1546 (2006)
- [c179]Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna: Generation of shorter sequences for high resolution error diagnosis using sequential SAT. ASP-DAC 2006: 25-29
- [c178]Kai Yang, Kwang-Ting Cheng: Efficient identification of multi-cycle false path. ASP-DAC 2006: 360-365
- [c177]Qiang Zhu, Mei-Chen Yeh, Kwang-Ting Cheng, Shai Avidan: Fast Human Detection Using a Cascade of Histograms of Oriented Gradients. CVPR (2) 2006: 1491-1498
- [c176]Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei: Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. DAC 2006: 1083-1088
- [c175]
- [c174]Yung-Chieh Lin, Kwang-Ting Cheng: Multiple-fault diagnosis based on single-fault activation and single-output observation. DATE 2006: 424-429
- [c173]Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng: Coverage loss by using space compactors in presence of unknown values. DATE 2006: 1053-1054
- [c172]Feng Lu, Kwang-Ting Cheng: IChecker: An Efficient Checker for Inductive Invariants. HLDVT 2006: 176-180
- [c171]Dongwoo Hong, Kwang-Ting Cheng: Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links. ITC 2006: 1-10
- [c170]Yung-Chieh Lin, Kwang-Ting Cheng: A Unified Approach to Test Generation and Test Data Volume Reduction. ITC 2006: 1-10
- [c169]Mitchell Lin, Kwang-Ting Cheng: Testable Design for Adaptive Linear Equalizer in High-Speed Serial Links. ITC 2006: 1-10
- [c168]Qiang Zhu, Mei-Chen Yeh, Kwang-Ting Cheng: Multimodal fusion using learned text concepts for image categorization. ACM Multimedia 2006: 211-220
- 2005
- [j52]Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin: Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator. ACM Trans. Design Autom. Electr. Syst. 10(4): 627-650 (2005)
- [c167]Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Cheng: Constraint extraction for pseudo-functional scan-based delay testing. ASP-DAC 2005: 166-171
- [c166]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer: Structural search for RTL with predicate learning. DAC 2005: 451-456
- [c165]Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng: Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. DATE 2005: 666-671
- [c164]Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen: An Efficient Sequential SAT Solver With Improved Search Strategies. DATE 2005: 1102-1107
- [c163]Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng: Simulation-based functional test generation for embedded processors. HLDVT 2005: 3-10
- [c162]Feng Lu, Kwang-Ting (Tim) Cheng: Sequential equivalence checking based on k-th invariants and circuit SAT solving. HLDVT 2005: 45-51
- [c161]Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng: Response shaper: a novel technique to enhance unknown tolerance for output response compaction. ICCAD 2005: 80-87
- [c160]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer: RTL SAT simplification by Boolean and interval arithmetic reasoning. ICCAD 2005: 297-302
- [c159]Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng: ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. ICCD 2005: 147-152
- [c158]Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng: Accurate Diagnosis of Multiple Faults. ICCD 2005: 153-156
- [c157]Qiang Zhu, Shai Avidan, Kwang-Ting Cheng: Learning a Sparse, Corner-Based Representation for Time-varying Background Modeling. ICCV 2005: 678-685
- [c156]Ching-Tung Wu, Kwang-Ting Cheng, Qiang Zhu, Yi-Leh Wu: Using visual features for anti-spam filtering. ICIP (3) 2005: 509-512
- [c155]Mitchell Lin, Kwang-Ting Cheng, Jimmy Hsu, M. C. Sun, Jason Chen, Shelton Lu: Production-oriented interface testing for PCI-Express by enhanced loop-back technique. ITC 2005: 10
- [c154]Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Wei-Ting Liu, Ji-Jan Chen: Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology. ITC 2005: 10
- [c153]Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen: On A Software-Based Self-Test Methodology and Its Application. VTS 2005: 107-113
- [c152]Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng: Pseudo-Functional Scan-based BIST for Delay Fault. VTS 2005: 229-234
- 2004
- [j51]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang: Safety Property Verification Using Sequential SAT and Bounded Model Checking. IEEE Design & Test of Computers 21(2): 132-143 (2004)
- [j50]T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang: New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. IEEE Design & Test of Computers 21(3): 241-247 (2004)
- [j49]Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna: A Signal Correlation Guided Circuit-SAT Solver. J. UCS 10(12): 1629-1654 (2004)
- [j48]Ying-Tsai Chang, Kwang-Ting Cheng: Self-referential verification for gate-level implementations of arithmetic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1102-1112 (2004)
- [j47]Li-C. Wang, Jing-Jia Liou, Kwang-Ting Cheng: Critical path selection for delay fault testing based upon a statistical timing model. IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1550-1565 (2004)
- [c151]Kai Yang, Kwang-Ting Cheng, Li-C. Wang: TranGen: a SAT-based ATPG for path-oriented transition faults. ASP-DAC 2004: 92-97
- [c150]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang: Jitter spectral extraction for multi-gigahertz signal. ASP-DAC 2004: 298-303
- [c149]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang: Efficient reachability checking using sequential SAT. ASP-DAC 2004: 418-423
- [c148]Tao Feng, Li-C. Wang, Kwang-Ting Cheng: Improved symbolic simulation by functional-space decomposition. ASP-DAC 2004: 634-639
- [c147]Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng: A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. Asian Test Symposium 2004: 62-67
- [c146]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang: An efficient finite-domain constraint solver for circuits. DAC 2004: 212-217
- [c145]Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir: On path-based learning and its applications in delay test and diagnosis. DAC 2004: 492-497
- [c144]Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin: Improved Symoblic Simulation by Dynamic Funtional Space Partitioning. DATE 2004: 42-49
- [c143]Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng: Pattern Selection for Testing of Deep Sub-Micron Timing Defects. DATE 2004: 160
- [c142]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang: Random Jitter Extraction Technique in a Multi-Gigahertz Signal. DATE 2004: 286-291
- [c141]Qiang Zhu, Kwang-Ting Cheng, Ching-Tung Wu, Yi-Leh Wu: Adaptive Learning of an Accurate Skin-Color Model. FGR 2004: 37-42
- [c140]Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Andy Lin: On using a 2-domain partitioned OBDD data structure in verification. HLDVT 2004: 49-54
- [c139]Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu: Static statistical timing analysis for latch-based pipeline designs. ICCAD 2004: 468-472
- [c138]Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng: A path-based methodology for post-silicon timing validation. ICCAD 2004: 713-720
- [c137]Qiang Zhu, Kwang-Ting Cheng, Ching-Tung Wu: A unified adaptive approach to accurate skin detection. ICIP 2004: 1189-1192
- [c136]Qiang Zhu, Kwang-Ting Cheng, HongJiang Zhang: SSD tracking using dynamic template and log-polar transformation. ICME 2004: 723-726
- [c135]Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng: BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics. ITC 2004: 1138-1147
- [c134]Qiang Zhu, Ching-Tung Wu, Kwang-Ting Cheng, Yi-Leh Wu: An adaptive skin model and its application to objectionable image filtering. ACM Multimedia 2004: 56-63
- [c133]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang: A Scalable On-Chip Jitter Extraction Technique. VTS 2004: 267-272
- 2003
- [j46]Li-C. Wang, Tao Feng, Kwang-Ting (Tim) Cheng, Magdy S. Abadir, Manish Pandey: Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems. Design Autom. for Emb. Sys. 8(2-3): 173-188 (2003)
- [j45]Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang: Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs. IEEE Design & Test of Computers 20(5): 6-7 (2003)
- [j44]Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng: Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 756-769 (2003)
- [c132]Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, Magdy S. Abadir: Enhanced symbolic simulation for efficient verification of embedded array systems. ASP-DAC 2003: 302-307
- [c131]Chee-Kian Ong, Kwang-Ting (Tim) Cheng, Li-C. Wang: Delta-sigma modulator based mixed-signal BIST architecture for SoC. ASP-DAC 2003: 669-674
- [c130]Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting Cheng: Experience in critical path selection for deep sub-micron delay test and timing validation. ASP-DAC 2003: 751-756
- [c129]Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna: A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. DAC 2003: 436-441
- [c128]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak: Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. DAC 2003: 668-673
- [c127]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir: Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. DATE 2003: 10328-10335
- [c126]Feng Lu, Li-C. Wang, Kwang-Ting Cheng, Ric C.-Y. Huang: A Circuit SAT Solver With Signal Correlation Guided Learning. DATE 2003: 10892-10897
- [c125]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang: A comparison of BDDs, BMC, and sequential SAT for model checking. HLDVT 2003: 157-162
- [c124]Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng: SATORI - A Fast Sequential SAT Engine for Circuits. ICCAD 2003: 320-325
- [c123]Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang: On Structural vs. Functional Testing for Delay Faults. ISQED 2003: 438-441
- [c122]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak: Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. ITC 2003: 339-348
- [c121]Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir: Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC 2003: 1041-1050
- [c120]
- [c119]Kaushik Roy, T. M. Mak, Kwang-Ting Cheng: Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. VTS 2003: 313-318
- [c118]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou: Diagnosis of Delay Defects Using Statistical Timing Models. VTS 2003: 339-344
- 2002
- [j43]Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey: Embedded Software-Based Self-Test for Programmable Core-Based Designs. IEEE Design & Test of Computers 19(4): 18-27 (2002)
- [c117]Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu: On-chip Analog Response Extraction with 1-Bit ? - Modulators. Asian Test Symposium 2002: 49-
- [c116]Ying-Tsai Chang, Kwang-Ting Cheng: Self-referential verification of gate-level implementations of arithmetic circuits. DAC 2002: 311-316
- [c115]Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey: Embedded software-based self-testing for SoC design. DAC 2002: 355-360
- [c114]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams: Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC 2002: 371-374
- [c113]Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng: False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. DAC 2002: 566-569
- [c112]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng: On theoretical and practical considerations of path selection for delay fault testing. ICCAD 2002: 94-100
- [c111]Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir: Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. ITC 2002: 203-212
- [c110]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams: Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC 2002: 407-416
- [c109]Wei-Cheng Lai, Chengwei Chang, Edward Y. Chang, Kwang-Ting Cheng, Michael Crandell: PBIR-MM: multimodal image retrieval and annotation. ACM Multimedia 2002: 421-422
- [c108]Yi-Leh Wu, Edward Y. Chang, Kwang-Ting Cheng, Chengwei Chang, Chen-Cha Hsu, Wei-Cheng Lai, Ching-Tung Wu: MORF: A Distributed Multimodal Information Filtering System. IEEE Pacific Rim Conference on Multimedia 2002: 279-286
- [c107]Wei-Cheng Lai, Edward Y. Chang, Kwang-Ting Cheng: Hybrid Learning Schemes for Multimedia Information Retrieval. IEEE Pacific Rim Conference on Multimedia 2002: 556-563
- [c106]Chee-Kian Ong, Kwang-Ting (Tim) Cheng: Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus. VTS 2002: 123-128
- [c105]Madhu K. Iyer, Kwang-Ting Cheng: Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. VTS 2002: 139-144
- 2001
- [j42]Chung-Yang Huang, Kwang-Ting Cheng: Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 381-391 (2001)
- [j41]Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng: Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 416-425 (2001)
- [j40]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: Verifying sequential equivalence using ATPG techniques. ACM Trans. Design Autom. Electr. Syst. 6(2): 244-275 (2001)
- [j39]Yi-Min Jiang, Kwang-Ting Cheng: Vector generation for power supply noise estimation and verification of deep submicron designs. IEEE Trans. VLSI Syst. 9(2): 329-340 (2001)
- [c104]Kingshy Goh, Edward Y. Chang, Kwang-Ting Cheng: SVM Binary Classifier Ensembles for Image Classification. CIKM 2001: 395-402
- [c103]Wei-Cheng Lai, Kwang-Ting Cheng: Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip. DAC 2001: 59-64
- [c102]Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic: Fast Statistical Timing Analysis By Probabilistic Event Propagation. DAC 2001: 661-666
- [c101]Ganapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng: An analysis of ATPG and SAT algorithms for formal verification. HLDVT 2001: 177-182
- [c100]Ying-Tsai Chang, Kwang-Ting Cheng: Induction-Based Gate-Level Verification of Multipliers. ICCAD 2001: 190-
- [c99]Beitao Li, Wei-Cheng Lai, Edward Y. Chang, Kwang-Ting Cheng: Mining Image Features for Efficient Query Processing. ICDM 2001: 353-360
- [c98]Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng: HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. ISQED 2001: 307-312
- [c97]Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng: Delay testing considering crosstalk-induced effects. ITC 2001: 558-567
- [c96]Edward Y. Chang, Kwang-Ting Cheng, Wei-Cheng Lai, Ching-Tung Wu, Chengwei Chang, Yi-Leh Wu: PBIR: perception-based image retrieval-a system that can quickly capture subjective image query concepts. ACM Multimedia 2001: 611-614
- [c95]Edward Y. Chang, Kwang-Ting (Tim) Cheng, Lihyuarn L. Chang: PBIR - Perception-Based Image Retrieval. SIGMOD Conference 2001: 613
- [c94]Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng: A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. VTS 2001: 198-203
- [c93]Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng: Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. VTS 2001: 204-209
- [c92]Jiun-Lang Huang, Kwang-Ting Cheng: An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. VTS 2001: 380-387
- 2000
- [j38]Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng: Functionally Testable Path Delay Faults on a Microprocessor. IEEE Design & Test of Computers 17(4): 6-14 (2000)
- [j37]Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Cheng: Testable Path Delay Fault Cover for Sequential Circuits. J. Inf. Sci. Eng. 16(5): 673-686 (2000)
- [j36]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer: AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49(5): 443-464 (2000)
- [j35]Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik: On improving test quality of scan-based BIST. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 928-938 (2000)
- [j34]Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng: Estimation for maximum instantaneous current through supply lines for CMOS circuits. IEEE Trans. VLSI Syst. 8(1): 61-73 (2000)
- [c91]Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu: Performance sensitivity analysis using statistical method and its applications to delay. ASP-DAC 2000: 587-592
- [c90]Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal: A testability metric for path delay faults and its application. ASP-DAC 2000: 593-598
- [c89]Jiun-Lang Huang, Kwang-Ting Cheng: A sigma-delta modulation based BIST scheme for mixed-signal circuits. ASP-DAC 2000: 605-612
- [c88]Vishwani D. Agrawal, Kwang-Ting Cheng: Testing in the Fourth Dimension. Asian Test Symposium 2000: 2-
- [c87]Melvin A. Breuer, Kwang-Ting Cheng: Challenges for the Academic Test Community. Asian Test Symposium 2000: 4-
- [c86]Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu: Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17-
- [c85]Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu: An FPGA-based re-configurable functional tester for memory chips. Asian Test Symposium 2000: 51-57
- [c84]Chung-Yang Huang, Kwang-Ting Cheng: Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. DAC 2000: 118-123
- [c83]Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy: Test challenges for deep sub-micron technologies. DAC 2000: 142-149
- [c82]Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng: A BIST Scheme for On-Chip ADC and DAC Testing. DATE 2000: 216-220
- [c81]Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng: Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. ICCAD 2000: 493-496
- [c80]Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng: Dynamic Timing Analysis Considering Power Supply Noise Effects. ISQED 2000: 137-144
- [c79]Subrata Roy, Gokhan Guner, Kwang-Ting Cheng: Efficient test mode selection and insertion for RTL-BIST. ITC 2000: 263-272
- [c78]Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng: Static property checking using ATPG vs. BDD techniques. ITC 2000: 309-316
- [c77]Jiun-Lang Huang, Kwang-Ting Cheng: Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. ITC 2000: 1021-1030
- [c76]Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng: Test program synthesis for path delay faults in microprocessor cores. ITC 2000: 1080-1089
- [c75]Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng: On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. VTS 2000: 15-22
- [c74]Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee: Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. VTS 2000: 97-104
- [c73]Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng: Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. VTS 2000: 237-246
1990 – 1999
- 1999
- [j33]Kwang-Ting Cheng, Angela Krstic: Current Directions in Automatic Test-Pattern Generation. IEEE Computer 32(11): 58-64 (1999)
- [j32]Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar: Primitive delay faults: identification, testing, and design for testability. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 669-684 (1999)
- [j31]Shi-Yu Huang, Kwang-Ting Cheng: ErrorTracer: design error diagnosis based on fault simulation techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1341-1352 (1999)
- [j30]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: AutoFix: a hybrid tool for automatic logic rectification. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1376-1384 (1999)
- [j29]Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai: Fault emulation: A new methodology for fault grading. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1487-1495 (1999)
- [c72]Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik: Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme. DAC 1999: 748-753
- [c71]Yi-Min Jiang, Kwang-Ting Cheng: Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices. DAC 1999: 760-765
- [c70]Yi-Min Jiang, Tak K. Young, Kwang-Ting Cheng: VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs. ISLPED 1999: 156-161
- [c69]Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng: Delay testing considering power supply noise effects. ITC 1999: 181-190
- [c68]Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar: Testing High Speed VLSI Devices Using Slower Testers. VTS 1999: 16-21
- [c67]Jiun-Lang Huang, Chen-Yang Pan, Kwang-Ting Cheng: Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. VTS 1999: 220-225
- [c66]
- 1998
- [j28]David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska: A hybrid methodology for switching activities estimation. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 357-366 (1998)
- [j27]Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee: Test-point insertion: scan paths through functional logic. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 838-851 (1998)
- [j26]Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik: Efficient test-point selection for scan-based BIST. IEEE Trans. VLSI Syst. 6(4): 667-676 (1998)
- [c65]Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho: A Hybrid Power Model for RTL Power Estimation. ASP-DAC 1998: 551-556
- [c64]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu: Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. DAC 1998: 632-637
- [c63]Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee: Functional Scan Chain Testing. DATE 1998: 278-283
- [c62]Yi-Min Jiang, Kwang-Ting Cheng: Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits. DATE 1998: 698-702
- [c61]Yi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng: Estimation of maximum power supply noise for deep sub-micron designs. ISLPED 1998: 233-238
- [c60]Chung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng: LIBRA - a library-independent framework for post-layout performance optimization. ISPD 1998: 135-140
- [c59]Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng: An almost full-scan BIST solution-higher fault coverage and shorter test application time. ITC 1998: 1065-1073
- 1997
- [j25]Kwang-Ting Cheng, Kewal K. Saluja, Hans-Joachim Wunderlich: Guest Editorial. J. Electronic Testing 11(1): 7-8 (1997)
- [j24]Angela Krstic, Kwang-Ting Cheng: Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability. J. Electronic Testing 11(1): 43-54 (1997)
- [j23]Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska: Postlayout logic restructuring using alternative wires. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 587-596 (1997)
- [j22]Chen-Yang Pan, Kwang-Ting Cheng: Pseudorandom testing for mixed-signal circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1173-1185 (1997)
- [c58]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: AQUILA: An equivalence verifier for large sequential circuits. ASP-DAC 1997: 455-460
- [c57]Angela Krstic, Kwang-Ting Cheng: Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits. DAC 1997: 383-388
- [c56]Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng: A Test Synthesis Approach to Reducing BALLAST DFT Overhead. DAC 1997: 466-471
- [c55]Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik: A Hybrid Algorithm for Test Point Selection for Scan-Based BIST. DAC 1997: 478-483
- [c54]Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska: Post-Layout Logic Restructuring for Performance Optimization. DAC 1997: 662-665
- [c53]Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar: Design for Primitive Delay Fault Testability. ITC 1997: 436-445
- [c52]Jiun-Lang Huang, Kwang-Ting Cheng: Analog Fault Diagnosis for Unpowered Circuit Boards. ITC 1997: 640-648
- [c51]Chen-Yang Pan, Kwang-Ting Cheng: Fault Macromodeling for Analog/Mixed-Signal Circuits. ITC 1997: 913-922
- [c50]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng: Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. ITC 1997: 974-981
- [c49]Kwang-Ting Cheng: National Science Foundation Workshop on Future Research Directions in Testing of Electronic Circuits and Systems: executive summary of workshop report. ITC 1997: 1157-1161
- [c48]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: Incremental logic rectification. VTS 1997: 143-149
- 1996
- [j21]Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta: Fault macromodeling and a testing strategy for opamps. J. Electronic Testing 9(3): 225-235 (1996)
- [j20]Kwang-Ting Cheng, Angela Krstic, Hsi-Chuan Chen: Generation of High Quality Tests for Robustly Untestable Path Delay Faults. IEEE Trans. Computers 45(12): 1379-1392 (1996)
- [j19]Kwang-Ting Cheng, Hsi-Chuan Chen: Classification and identification of nonrobust untestable path delay faults. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 845-853 (1996)
- [j18]Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: Perturb and simplify: multilevel Boolean network optimizer. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1494-1504 (1996)
- [j17]Kwang-Ting Cheng, A. S. Krishnakumar: Automatic generation of functional vectors using the extended finite state machine model. ACM Trans. Design Autom. Electr. Syst. 1(1): 57-79 (1996)
- [j16]Kwang-Ting Cheng: Gate-level test generation for sequential circuits. ACM Trans. Design Autom. Electr. Syst. 1(4): 405-442 (1996)
- [c47]Hisashi Kondo, Kwang-Ting Cheng: An Efficient Compact Test Generator for IDDQ Testing. Asian Test Symposium 1996: 177-182
- [c46]Kwang-Ting Cheng: Built-In Self Test for Analog and Mixed-Signal Designs. Asian Test Symposium 1996: 197-198
- [c45]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee: Compact Vector Generation for Accurate Power Simulation. DAC 1996: 161-164
- [c44]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: Error Correction Based on Verification Techniques. DAC 1996: 258-261
- [c43]Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee: Test Point Insertion: Scan Paths through Combinational Logic. DAC 1996: 268-273
- [c42]David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska: A New Hybrid Methodology for Power Estimation. DAC 1996: 439-444
- [c41]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: On Verifying the Correctness of Retimed Circuits. Great Lakes Symposium on VLSI 1996: 277-
- [c40]Hisashi Kondo, Kwang-Ting Cheng: Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG. ICCAD 1996: 228-232
- [c39]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee: A novel methodology for transistor-level power estimation. ISLPED 1996: 67-72
- [c38]Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar: Identification and Test Generation for Primitive Faults. ITC 1996: 423-432
- [c37]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser: An ATPG-Based Framework for Verifying Sequential Equivalence. ITC 1996: 865-874
- [c36]
- 1995
- [j15]Kwang-Ting (Tim) Cheng: Single-Clock Partial Scan. IEEE Design & Test of Computers 12(2): 24-31 (1995)
- [j14]Jing-Yang Jou, Kwang-Ting (Tim) Cheng: Timing-Driven Partial Scan. IEEE Design & Test of Computers 12(4): 52-59 (1995)
- [j13]Luis Entrena-Arrontes, Kwang-Ting Cheng: Combinational and sequential logic optimization by redundancy addition and removal. IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 909-916 (1995)
- [c35]Uwe Gläser, Kwang-Ting Cheng: Logic optimization by an improved sequential redundancy addition and removal techniques. ASP-DAC 1995
- [c34]Uwe Sparmann, D. Luxenburger, Kwang-Ting Cheng, Sudhakar M. Reddy: Fast Identification of Robust Dependent Path Delay Faults. DAC 1995: 119-125
- [c33]Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: Logic Synthesis for Engineering Change. DAC 1995: 647-652
- [c32]Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: An Efficient Algorithm for Local Don't Care Sets Calculation. DAC 1995: 663-667
- [c31]Chen-Yang Pan, Kwang-Ting Cheng: Pseudo-random testing and signature analysis for mixed-signal circuits. ICCAD 1995: 102-107
- [c30]Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai: Fault emulation: a new approach to fault grading. ICCAD 1995: 681-686
- [c29]Kwang-Ting Cheng, Chih-Jen Lin: Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST. ITC 1995: 506-514
- [c28]
- [c27]Angela Krstic, Kwang-Ting Cheng: Generation of high quality tests for functional sensitizable paths. VTS 1995: 374-379
- 1994
- [c26]Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska: Layout Driven Logic Synthesis for FPGAs. DAC 1994: 308-313
- [c25]Kwang-Ting Cheng, Hsi-Chuan Chen: Generation of High Quality Non-Robust Tests for Path Delay Faults. DAC 1994: 365-369
- [c24]A. S. Krishnakumar, Kwang-Ting Cheng: On the Computation of the Set of Reachable States of Hybrid Models. DAC 1994: 615-621
- [c23]Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta: A comprehensive fault macromodel for opamps. ICCAD 1994: 344-348
- 1993
- [j12]Wayne Wei-Ming Dai, Kwang-Ting (Tim) Cheng: Guest Editor's Introduction. IEEE Design & Test of Computers 10(4): 7- (1993)
- [j11]Kwang-Ting Cheng: Redundancy removal for sequential circuits without reset states. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 13-24 (1993)
- [j10]Irith Pomeranz, Kwang-Ting Cheng: STOIC: state assignment based on output/input functions. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1123-1131 (1993)
- [j9]Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer: Delay-fault test generation and synthesis for testability under a standard scan design methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1217-1231 (1993)
- [j8]Kwang-Ting Cheng, Hi-Keung Tony Ma: On the over-specification problem in sequential ATPG algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1599-1604 (1993)
- [j7]Kwang-Ting Cheng: Transition fault testing for sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1971-1983 (1993)
- [c22]Kwang-Ting Cheng, A. S. Krishnakumar: Automatic Functional Test Generation Using the Extended Finite State Machine Model. DAC 1993: 86-91
- [c21]Luis Entrena, Kwang-Ting Cheng: Sequential logic optimization by redundancy addition and removal. ICCAD 1993: 310-315
- [c20]Kwang-Ting Cheng, Hsi-Chuan Chen: Delay Testing for Non-Robust Untestable Circuits. ITC 1993: 954-961
- 1992
- [j6]Kwang-Ting Cheng, Vishwani D. Agrawal: Initializability Consideration in Sequential Machine Synthesis. IEEE Trans. Computers 41(3): 374-379 (1992)
- [j5]Kwang-Ting Cheng, Jing-Yang Jou: A functional fault model for sequential machines. IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1065-1073 (1992)
- [c19]Kwang-Ting Cheng, Hi-Keung Tony Ma: On the Over-Specification Problem in Sequential ATPG Algorithms. DAC 1992: 16-21
- [c18]
- [c17]Kwang-Ting Cheng: Test generation for delay faults in non-scan and partial scan sequential circuits. ICCAD 1992: 554-559
- [c16]
- 1991
- [c15]Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer: Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology. DAC 1991: 80-86
- [c14]
- [c13]
- [c12]
- [c11]Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer: A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits. ITC 1991: 403-410
- 1990
- [j4]Vishwani D. Agrawal, Kwang-Ting Cheng: Finite state machine synthesis with embedded test function. J. Electronic Testing 1(3): 221-228 (1990)
- [j3]Kwang-Ting Cheng, Vishwani D. Agrawal: A Partial Scan Method for Sequential Circuits with Feedback. IEEE Trans. Computers 39(4): 544-549 (1990)
- [j2]Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh: A Simulation-Based Method for Generating Tests for Sequential Circuits. IEEE Trans. Computers 39(12): 1456-1463 (1990)
- [c10]
- [c9]Kwang-Ting Cheng, Vishwani D. Agrawal: An Entropy Measure for the Complexity of Multi-Output Boolean Functions. DAC 1990: 302-305
- [c8]Vishwani D. Agrawal, Kwang-Ting Cheng: An architecture for synthesis of testable finite state machines. EURO-DAC 1990: 612-616
- [c7]Kwang-Ting Cheng, Jing-Yang Jou: A Single-State-Transition Fault Model for Sequential Machines. ICCAD 1990: 226-229
- [c6]Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng: Timing Optimization with Testability Considerations. ICCAD 1990: 460-463
- [c5]Kwang-Ting Cheng, Jing-Yang Jou: Functional test generation for finite state machines. ITC 1990: 162-168
1980 – 1989
- 1989
- [j1]Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal: A directed search method for test generation using a concurrent simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 131-138 (1989)
- [c4]Kwang-Ting Cheng, Vishwani D. Agrawal: An economical scan design for sequential logic test generation. FTCS 1989: 28-35
- [c3]Prathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, R. Tutundjian: Fault Simulation in a Pipelined Multiprocessor System. ITC 1989: 727-734
- 1988
- [c2]Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal: Contest: A Concurrent Test Generator for Sequential Circuits. DAC 1988: 84-89
- [c1]Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh: A sequential circuit test generation using threshold-value simulation. FTCS 1988: 24-29
Coauthor Index