Wu-Tung Cheng

Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai: Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 32(5): 737-747 (2013)

Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang: Scan-Based Speed-Path Debug for a Microprocessor. IEEE Design & Test of Computers 29(4): 92-99 (2012)

Xiaoxin Fan, Manish Sharma, Wu-Tung Cheng, Sudhakar M. Reddy: Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns. ATS 2012: 7-12

Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng: Programmable Leakage Test and Binning for TSVs. ATS 2012: 43-48

Wu-Tung Cheng, Feng-Ming Kuo: Embedded Tutorial Summary: Diagnosis for Accelerating Yield and Failure Analysis. ATS 2012: 271

Jianbo Li, Yu Huang, Wu-Tung Cheng, Chris Schuermyer, Dong Xiang, Eric Faehn, Ruth Farrugia: A Hybrid Flow for Memory Failure Bitmap Classification. ATS 2012: 314-319

Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai: Small delay testing for TSVs in 3-D ICs. DAC 2012: 1031-1036

Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware: Improved volume diagnosis throughput using dynamic design partitioning. ITC 2012: 1-10

Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter: A unified method for parametric fault characterization of post-bond TSVs. ITC 2012: 1-10

Xiaoxin Fan, Huaxing Tang, Sudhakar M. Reddy, Wu-Tung Cheng, Brady Benware: On Using Design Partitioning to Reduce Diagnosis Memory Footprint. Asian Test Symposium 2011: 219-225

Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Huaxing Tang, Sudhakar M. Reddy: Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree. DFT 2011: 217-225

Andras Kun, Ralf Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng: Deterministic IDDQ diagnosis using a net activation based model. ITC 2011: 1-10

Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab: A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores. ITC 2011: 1-9

Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak: On Reducing Scan Shift Activity at RTL. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1110-1120 (2010)

Meng-Fan Wu, Hsin-Cheih Pan, T.-H. Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng: Improved weight assignment for logic switching activity during at-speed test pattern generation. ASP-DAC 2010: 493-498

Ke Peng, Yu Huang, Ruifeng Guo, Wu-Tung Cheng, Mohammad Tehranipoor: Emulating and diagnosing IR-drop by using dynamic SDF. ASP-DAC 2010: 511-516

Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Sudhakar M. Reddy: Diagnosis of Multiple Physical Defects Using Logic Fault Models. Asian Test Symposium 2010: 94-99

Wu-Tung Cheng, Yu Huang: Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking. Asian Test Symposium 2010: 255-260

Ke Peng, Yu Huang, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor: Full-circuit SPICE simulation based validation of dynamic delay estimation. European Test Symposium 2010: 101-106

Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz: Scan based speed-path debug for a microprocessor. European Test Symposium 2010: 207-212

Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli: A scalable quantitative measure of IR-drop effects for scan pattern generation. ICCAD 2010: 162-167

Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli: Test cycle power optimization for scan-based designs. ITC 2010: 134-143

Yu Huang, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen: Case study of scan chain diagnosis and PFA on a low yield wafer. ITC 2010: 818

Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen: Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns. Asian Test Symposium 2009: 35-40

Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang: On Improving Diagnostic Test Generation for Scan Chain Failures. Asian Test Symposium 2009: 41-46

Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng: At-Speed Scan Test Method for the Timing Optimization and Calibration. Asian Test Symposium 2009: 430-433

Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy: Improving compressed test pattern generation for multiple scan chain failure diagnosis. DATE 2009: 1000-1005

Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai: Speed-Path Debug Using At-Speed Scan Test Patterns. European Test Symposium 2009: 11-16

Yu Huang, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li: Survey of Scan Chain Diagnosis. IEEE Design & Test of Computers 25(3): 240-248 (2008)

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab: X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 147-159 (2008)

Yu Huang, Wu-Tung Cheng, Ruifeng Guo: Diagnose Multiple Stuck-at Scan Chain Faults. European Test Symposium 2008: 105-110

Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng: Detection and Diagnosis of Static Scan Cell Internal Defect. ITC 2008: 1-10

Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng: Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. ITC 2008: 1-10

Manish Sharma, Brady Benware, Lei Ling, David Abercrombie, Lincoln Lee, Martin Keim, Huaxing Tang, Wu-Tung Cheng, Ting-Pu Tai, Yi-Jung Chang, Reinhart Lin, Albert Mann: Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data. ITC 2008: 1-9

Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak: Reducing Scan Shift Power at RTL. VTS 2008: 139-146

Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng: Automatic Test Pattern Generation for Interconnect Open Defects. VTS 2008: 181-186

Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai: X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Design & Test of Computers 24(5): 476-485 (2007)

Ruifeng Guo, Yu Huang, Wu-Tung Cheng: A complete test set to diagnose scan chain failures. ITC 2007: 1-10

Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Will Hsu, Yuan-Shih Chen, Albert Mann: Diagnose compound scan chain and system logic defects. ITC 2007: 1-10

Chen Liu, Wei Zou, Sudhakar M. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang: Interconnect open defect diagnosis with minimal physical information. ITC 2007: 1-10

Manish Sharma, Wu-Tung Cheng, Ting-Pu Tai, Y. S. Cheng, Will Hsu, Chen Liu, Sudhakar M. Reddy, Albert Mann: Faster defect localization in nanometer technology based on defective cell diagnosis. ITC 2007: 1-10

Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang: Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. VTS 2007: 225-230

Wu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill: Signature Based Diagnosis for Logic BIST. ITC 2006: 1-9

Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen: Diagnosis with Limited Failure Information. ITC 2006: 1-10

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab: X-Press Compactor for 1000x Reduction of Test Data. ITC 2006: 1-10

Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich: Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. ITC 2006: 1-9

Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang: On Methods to Improve Location Based Logic Diagnosis. VLSI Design 2006: 181-187

Yu Huang, Wu-Tung Cheng, Greg Crowell: Using fault model relaxation to diagnose real scan chain defects. ASP-DAC 2005: 1176-1179

Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy: Bridge Defect Diagnosis with Physical Information. Asian Test Symposium 2005: 248-253

Jay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press: Achieving High Test Quality with Reduced Pin Count Testing. Asian Test Symposium 2005: 312-317

Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng: Hardware Ef.cient LBISTWith Complementary Weights. ICCD 2005: 479-484

Yu Huang, Wu-Tung Cheng, Janusz Rajski: Compressed pattern diagnosis for scan chain failures. ITC 2005: 8

Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy: Full-speed field-programmable memory BIST architecture. ITC 2005: 9

Manish Sharma, Wu-Tung Cheng: X-filter: filtering unknowns from compacted test responses. ITC 2005: 9

Andreas Leininger, Peter Muhmenthaler, Wu-Tung Cheng, Nagesh Tamarapalli, Wu Yang, Hans Tsai: Compression mode diagnosis enables high volume monitoring diagnosis flow. ITC 2005: 10

Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski: Compactor Independent Direct Diagnosis. Asian Test Symposium 2004: 204-209

Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung: Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis. DATE 2004: 1072-1077

Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng: Logic BIST with Scan Chain Segmentation. ITC 2004: 57-66

Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee: At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. VLSI Design 2004: 895-900

Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel: Logic BIST Using Constrained Scan Cells. VTS 2004: 199-205

Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk: Memory BIST Using ESP. VTS 2004: 243-248

Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung: Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults. Asian Test Symposium 2003: 44-49

Xiaogang Du, Sudhakar M. Reddy, Joseph Rayhawk, Wu-Tung Cheng: Testing Delay Faults in Embedded CAMs. Asian Test Symposium 2003: 378-383

Yu Huang, Wu-Tung Cheng: Using embedded infrastructure IP for SOC post-silicon verification. DAC 2003: 674-677

Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy: Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. ISQED 2003: 99-104

Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung: Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. ITC 2003: 319-328

Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai: BIST for Deep Submicron ASIC Memories with High Performance Application. ITC 2003: 386-392

Wu-Tung Cheng: Silicon Diagnosis. ITC 2003: 1305

Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy: Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electronic Testing 18(2): 189-201 (2002)

Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: On Concurrent Test of Core-Based SOC Design. J. Electronic Testing 18(4-5): 401-414 (2002)

Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng: Core - Clustering Based SOC Test Scheduling Optimization. Asian Test Symposium 2002: 405-410

Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan: Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. ITC 2002: 74-82

Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy: Constraint Driven Pin Mapping for Concurrent SOC Testing. VLSI Design 2002: 511-516

Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Asian Test Symposium 2001: 265-

Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy: On RTL scan design. ITC 2001: 728-737

Wu-Tung Cheng: Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. Asian Test Symposium 2000: 10-

Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy: SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS 2000: 205-212

Wu-Tung Cheng: High time for high level ATPG. ITC 1999: 1113

Bejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski: A Universal Technique for Accelerating Simulation of Scan Test Patterns. ITC 1996: 135-141

Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel: PROOFS: a fast, memory-efficient sequential circuit fault simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 198-207 (1992)

Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu: Optimal diagnostic methods for wiring interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1161-1166 (1992)

Wu-Tung Cheng, Meng-Lin Yu: Differential fault simulation for sequential circuits. J. Electronic Testing 1(1): 7-13 (1990)

Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel: Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. DAC 1990: 535-540

Wu-Tung Cheng, Janak H. Patel: PROOFS: a super fast fault simulator for sequential circuits. EURO-DAC 1990: 475-479

Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu: Diagnosis for wiring interconnects. ITC 1990: 565-571

Wu-Tung Cheng, Tapan J. Chakraborty: Gentest: An Automatic Test-Generation System for Sequential Circuits. IEEE Computer 22(4): 43-49 (1989)

Wu-Tung Cheng, Meng-Lin Yu: Differential Fault Simulation - a Fast Method Using Minimal Memory. DAC 1989: 424-428

Wu-Tung Cheng: Split Circuit Model for Test Generation. DAC 1988: 96-101

Wu-Tung Cheng, Janak H. Patel: A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders. IEEE Trans. Computers 36(7): 891-895 (1987)

Wu-Tung Cheng, Janak H. Patel: Multiple-Fault Detection in Iterative Logic Arrays. ITC 1985: 493-499