| 2013 | ||
|---|---|---|
| c171 | Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski: Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. ARC 2013: 1-12 | |
| 2012 | ||
| j44 | Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung: Roberts: reconfigurable platform for benchmarking real-time systems. SIGARCH Computer Architecture News 40(5): 10-15 (2012) | |
| c170 | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung: Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. FCCM 2012: 109-116 | |
| c169 | Zhenyu Guan, Justin S. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung: A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL 2012: 519-522 | |
| c168 | Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski: Adaptive Sequential Monte Carlo approach for real-time applications. FPL 2012: 527-530 | |
| c167 | Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung: Early performance estimation of image compression methods on soft processors. FPL 2012: 587-590 | |
| 2011 | ||
| j43 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. Comput. J. 54(1): 1-10 (2011) | |
| j42 | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung: Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array. IET Computers & Digital Techniques 5(4): 271-286 (2011) | |
| j41 | Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes: A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors. T. HiPEAC 4: 63-83 (2011) | |
| j40 | Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk: Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Transactions on Industrial Electronics 58(8): 3701-3716 (2011) | |
| j39 | ||
| c166 | Justin S. Wong, Peter Y. K. Cheung: Improved delay measurement method in FPGA based on transition probability. FPGA 2011: 163-172 | |
| c165 | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung: Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). FPGA 2011: 284 | |
| c164 | Edward A. Stott, Peter Y. K. Cheung: Improving FPGA Reliability with Wear-Levelling. FPL 2011: 323-328 | |
| c163 | Sumanta Chaudhuri, Justin S. Wong, Peter Y. K. Cheung: Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. FPT 2011: 1-8 | |
| 2010 | ||
| j38 | Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung: Fault tolerance and reliability in field-programmable gate arrays. IET Computers & Digital Techniques 4(3): 196-210 (2010) | |
| j37 | Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa: Power Characterisation for Fine-Grain Reconfigurable Fabrics. Int. J. Reconfig. Comp. 2010 (2010) | |
| j36 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Wave-pipelined intra-chip signaling for on-FPGA communications. Integration 43(2): 188-201 (2010) | |
| j35 | Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes: Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study. IEEE Trans. Computers 59(4): 433-448 (2010) | |
| j34 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: FPGA Architecture Optimization Using Geometric Programming. IEEE Trans. on CAD of Integrated Circuits and Systems 29(8): 1163-1176 (2010) | |
| j33 | Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen: Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. ACM Trans. Design Autom. Electr. Syst. 15(2) (2010) | |
| j32 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays. TRETS 3(3): 13 (2010) | |
| j31 | Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. TRETS 4(1): 3 (2010) | |
| j30 | Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung: Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs. IEEE Trans. VLSI Syst. 18(3): 436-449 (2010) | |
| c162 | Peter Y. K. Cheung: Process Variability and Degradation: New Frontier for Reconfigurable. ARC 2010: 2 | |
| c161 | Sebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung: Exploration of hardware sharing for image encoders. DATE 2010: 1737-1742 | |
| c160 | Tobias Becker, Wayne Luk, Peter Y. K. Cheung: Energy-Aware Optimisation for Run-Time Reconfiguration. FCCM 2010: 55-62 | |
| c159 | Edward A. Stott, Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung: Degradation in FPGAs: measurement and modelling. FPGA 2010: 229-238 | |
| c158 | David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung: GPU Versus FPGA for High Productivity Computing. FPL 2010: 119-124 | |
| c157 | Edward A. Stott, Justin S. Wong, Peter Y. K. Cheung: Degradation Analysis and Mitigation in FPGAs. FPL 2010: 428-433 | |
| c156 | David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung: A Salient Region Detector for GPU Using a Cellular Automata Architecture. ICONIP (2) 2010: 501-508 | |
| e4 | Peter Y. K. Cheung, John Wawrzynek (Eds.): Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010. ACM 2010, isbn 978-1-60558-911-4 | |
| 2009 | ||
| j29 | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung: Hardware architectures for eigenvalue computation of real symmetric matrices. IET Computers & Digital Techniques 3(1): 72-84 (2009) | |
| j28 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. IET Computers & Digital Techniques 3(3): 235-246 (2009) | |
| j27 | Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk: High-throughput one-dimensional median and weighted median filters on FPGA. IET Computers & Digital Techniques 3(4): 384-394 (2009) | |
| j26 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 305-315 (2009) | |
| j25 | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung: Word-length selection for power minimization via nonlinear optimization. ACM Trans. Design Autom. Electr. Syst. 14(3) (2009) | |
| j24 | Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung: Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. TRETS 1(4) (2009) | |
| j23 | Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung: Self-Measurement of Combinatorial Circuit Delays in FPGAs. TRETS 2(2) (2009) | |
| j22 | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides: Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement. TRETS 2(4) (2009) | |
| c155 | Tobias Becker, Wayne Luk, Peter Y. K. Cheung: Parametric Design for Reconfigurable Software-Defined Radio. ARC 2009: 15-26 | |
| c154 | Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung: Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. ARC 2009: 133-144 | |
| c153 | Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam: A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS 2009: 119-128 | |
| c152 | Philip G. Potter, Wayne Luk, Peter Y. K. Cheung: Partition-based exploration for reconfigurable JPEG designs. DATE 2009: 886-889 | |
| c151 | Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen: Benchmarking Reconfigurable Architectures in the Mobile Domain. FCCM 2009: 131-138 | |
| c150 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Area estimation and optimisation of FPGA routing fabrics. FPL 2009: 256-261 | |
| c149 | N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung: Compensating for variability in FPGAs by re-mapping and re-placement. FPL 2009: 613-616 | |
| c148 | Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung: Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT 2009: 54-61 | |
| c147 | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung: A sensor-based approach to linear blur identification for real-time video enhancement. ICIP 2009: 141-144 | |
| c146 | Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung: Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. ISCAS 2009: 1293-1296 | |
| e3 | ||
| 2008 | ||
| j21 | Peter Y. K. Cheung, Alexandre Yakovlev: Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber. Comput. J. 51(6): 741-742 (2008) | |
| j20 | Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: Custom parallel caching schemes for hardware-accelerated image compression. J. Real-Time Image Processing 3(4): 289-302 (2008) | |
| j19 | Sutjipto Arifin, Peter Y. K. Cheung: Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance Information. IEEE Transactions on Multimedia 10(7): 1325-1341 (2008) | |
| j18 | N. Pete Sedcole, Peter Y. K. Cheung: Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. TRETS 1(2) (2008) | |
| j17 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. IEEE Trans. VLSI Syst. 16(6): 733-744 (2008) | |
| j16 | Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung: Outer Loop Pipelining for Application Specific Datapaths in FPGAs. IEEE Trans. VLSI Syst. 16(10): 1268-1280 (2008) | |
| j15 | Maria E. Angelopoulou, Kostas Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos: Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs. Signal Processing Systems 51(1): 3-21 (2008) | |
| c145 | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides: FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. ARC 2008: 124-135 | |
| c144 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. BCS Int. Acad. Conf. 2008: 295-304 | |
| c143 | ||
| c142 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA 2008: 258 | |
| c141 | N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Measuring and modeling FPGA clock variability. FPGA 2008: 258 | |
| c140 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. FPL 2008: 179-184 | |
| c139 | Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung: Fault tolerant methods for reliability in FPGAs. FPL 2008: 415-420 | |
| c138 | Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa: Towards benchmarking energy efficiency of reconfigurable architectures. FPL 2008: 691-694 | |
| c137 | Justin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole: Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL 2008: 703-704 | |
| c136 | Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos: Co-optimisation of datapath and memory in outer loop pipelining. FPT 2008: 1-8 | |
| c135 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Wave-pipelined signaling for on-FPGA communication. FPT 2008: 9-16 | |
| c134 | Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung: A transition probability based delay measurement method for arbitrary circuits on FPGAs. FPT 2008: 105-112 | |
| c133 | N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Modelling and compensating for clock skew variability in FPGAs. FPT 2008: 217-224 | |
| c132 | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung: Video enhancement on an adaptive image sensor. ICIP 2008: 681-684 | |
| c131 | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith: Glitch-aware output switching activity from word-level statistics. ISCAS 2008: 1792-1795 | |
| c130 | N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Characterisation of FPGA Clock Variability. ISVLSI 2008: 322-328 | |
| c129 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS 2008: 213-214 | |
| c128 | Ben Cope, Peter Y. K. Cheung, Wayne Luk: Systematic design space exploration for customisable multi-processor architectures. ICSAMOS 2008: 57-64 | |
| c127 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Interconnection lengths and delays estimation for communication links in FPGAs. SLIP 2008: 1-10 | |
| c126 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Global interconnections in FPGAs: modeling and performance analysis. SLIP 2008: 51-58 | |
| 2007 | ||
| j14 | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: ROM to DSP block transfer for resource constrained synthesis. IET Computers & Digital Techniques 1(1): 17-26 (2007) | |
| j13 | Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk: Real-time hardware acceleration of the trace transform. J. Real-Time Image Processing 2(4): 235-248 (2007) | |
| j12 | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. VLSI Syst. 15(9): 1003-1016 (2007) | |
| c125 | ||
| c124 | Tobias Becker, Wayne Luk, Peter Y. K. Cheung: Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. FCCM 2007: 35-44 | |
| c123 | Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung: Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs. FCCM 2007: 141-150 | |
| c122 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Automatic On-chip Memory Minimization for Data Reuse. FCCM 2007: 251-260 | |
| c121 | Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: A Hybrid Memory Sub-system for Video Coding Applications. FCCM 2007: 317-318 | |
| c120 | N. Pete Sedcole, Peter Y. K. Cheung: Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. FPGA 2007: 178-187 | |
| c119 | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung: On the feasibility of early routing capacitance estimation for FPGAs. FPL 2007: 234-239 | |
| c118 | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung: Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. FPL 2007: 345-350 | |
| c117 | Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung: Self-characterization of Combinatorial Circuit Delays in FPGAs. FPT 2007: 17-23 | |
| c116 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction. FPT 2007: 105-112 | |
| c115 | Sutjipto Arifin, Peter Y. K. Cheung: A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional Information. ICIP (6) 2007: 333-336 | |
| c114 | Sutjipto Arifin, Peter Y. K. Cheung: A computation method for video segmentation utilizing the pleasure-arousal-dominance emotional information. ACM Multimedia 2007: 68-77 | |
| c113 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam: A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS 2007: 173-182 | |
| c112 | Sutjipto Arifin, Peter Y. K. Cheung: A Novel Probabilistic Approach to Modeling the Pleasure-Arousal-Dominance Content of the Video based on "Working Memory". ICSC 2007: 147-154 | |
| 2006 | ||
| c111 | Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. ARC 2006: 205-216 | |
| c110 | Sutjipto Arifin, Peter Y. K. Cheung: A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation. DATE Designers' Forum 2006: 227-232 | |
| c109 | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley: Hardware efficient architectures for Eigenvalue computation. DATE 2006: 953-958 | |
| c108 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. FCCM 2006: 275-276 | |
| c107 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Yield enhancements of design-specific FPGAs. FPGA 2006: 93-100 | |
| c106 | Sutjipto Arifin, Peter Y. K. Cheung: Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System. FPL 2006: 1-4 | |
| c105 | Christos-Savvas Bouganis, Peter Y. K. Cheung, Zhaoping Li: FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex. FPL 2006: 1-6 | |
| c104 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. FPL 2006: 1-6 | |
| c103 | Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk: Efficient Realtime FPGA Implementation of the Trace Transform. FPL 2006: 1-6 | |
| c102 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: On-FPGA Communication Architectures and Design Factors. FPL 2006: 1-8 | |
| c101 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. FPL 2006: 1-6 | |
| c100 | N. Pete Sedcole, Peter Y. K. Cheung: Within-die delay variability in 90nm FPGAs and beyond. FPT 2006: 97-104 | |
| c99 | Maria E. Angelopoulou, Konstantinos Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos: A comparison of 2-D discrete wavelet transform computation schedules on FPGAs. FPT 2006: 181-188 | |
| c98 | Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: The cost of data dependence in motion vector estimation for reconfigurable platforms. FPT 2006: 333-336 | |
| c97 | Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung: A statistical framework for dimensionality reduction implementation in FPGAs. FPT 2006: 365-368 | |
| c96 | Sutjipto Arifin, Peter Y. K. Cheung: User Attention Based Arousal Content Modeling. ICIP 2006: 433-436 | |
| c95 | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung: A Spatiotemporal Saliency Framework. ICIP 2006: 437-440 | |
| c94 | Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung: Fast word-level power models for synthesis of FPGA-based arithmetic. ISCAS 2006 | |
| c93 | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS 2006: 168-176 | |
| 2005 | ||
| j11 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Optimum and heuristic synthesis of multiple word-length architectures. IEEE Trans. VLSI Syst. 13(1): 39-57 (2005) | |
| j10 | Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung: Customizable elliptic curve cryptosystems. IEEE Trans. VLSI Syst. 13(9): 1048-1059 (2005) | |
| c92 | Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung: Automating custom-precision function evaluation for embedded processors. CASES 2005: 22-31 | |
| c91 | Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk: Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. DATE 2005: 8-13 | |
| c90 | Ray C. C. Cheung, Wayne Luk, Peter Y. K. Cheung: Reconfigurable Elliptic Curve Cryptosystems on a Chip. DATE 2005: 24-29 | |
| c89 | Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen: Cell Based Motion Estimators for Reconfigurable Platforms. ERSA 2005: 218-224 | |
| c88 | Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung: A Novel 2D Filter Design Methodology for Heterogeneous Devices. FCCM 2005: 13-22 | |
| c87 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. FPGA 2005: 138-148 | |
| c86 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Exploration of heterogeneous reconfigurable architectures (abstract only). FPGA 2005: 268 | |
| c85 | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. FPL 2005: 77-82 | |
| c84 | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Power and Area Optimization for Multiple Restricted Multiplication. FPL 2005: 112-117 | |
| c83 | Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides: Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. FPL 2005: 124-129 | |
| c82 | Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk: Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. FPL 2005: 142-147 | |
| c81 | Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides: Heterogeneity Exploration for Multiple 2D Filter Designs. FPL 2005: 263-268 | |
| c80 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. FPL 2005: 341-346 | |
| c79 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. FPL 2005: 409-414 | |
| c78 | Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt: Have GPUs Made FPGAs Redundant in the Field of Video Processing? FPT 2005: 111-118 | |
| c77 | Laurence A. Hey, Peter Y. K. Cheung, Michael Gellman: FPGA Based Router for Cognitive Packet Networks. FPT 2005: 331-332 | |
| c76 | Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung: A novel 2D filter design methodology. ISCAS (1) 2005: 532-535 | |
| c75 | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: A heuristic approach for multiple restricted multiplication. ISCAS (1) 2005: 692-695 | |
| 2004 | ||
| b1 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthesis and optimization of DSP algorithms. Kluwer 2004, isbn 978-1-4020-7930-6, pp. I-XI, 1-164 | |
| j9 | Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa: Guest Editors' Introduction: Field Programmable Logic and Applications. IEEE Trans. Computers 53(11): 1361-1362 (2004) | |
| j8 | Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: A Gaussian Noise Generator for Hardware-Based Simulations. IEEE Trans. Computers 53(12): 1523-1534 (2004) | |
| c74 | Sambuddhi Hettiaratchi, Peter Y. K. Cheung: A Novel Implementation of Tile-Based Address Mapping. DATE 2004: 306-311 | |
| c73 | Tero Rissa, Wayne Luk, Peter Y. K. Cheung: Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. ERSA 2004: 184-193 | |
| c72 | Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung: Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. FCCM 2004: 79-88 | |
| c71 | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM 2004: 271-272 | |
| c70 | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: Migrating Functionality from ROMS to Embedded Multipliers. FCCM 2004: 287-288 | |
| c69 | Tero Rissa, Peter Y. K. Cheung, Wayne Luk: SoftSONIC: A Customisable Modular Platform for Video Applications. FPL 2004: 54-63 | |
| c68 | Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides: Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. FPL 2004: 200-208 | |
| c67 | Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko: BIST Based Interconnect Fault Location for FPGAs. FPL 2004: 322-332 | |
| c66 | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Multiple Restricted Multiplication. FPL 2004: 374-383 | |
| c65 | Christos-Savvas Bouganis, Peter Y. K. Cheung, Jeffrey Ng, Anil A. Bharath: A Steerable Complex Wavelet Construction and Its Implementation on FPGA. FPL 2004: 394-403 | |
| c64 | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured Methodology for System-on-an-FPGA Design. FPL 2004: 1047-1051 | |
| c63 | Ray C. C. Cheung, Ashley Brown, Wayne Luk, Peter Y. K. Cheung: A scalable hardware architecture for prime number validation. FPT 2004: 177-184 | |
| c62 | Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Scalable structured data access by combining autonomous memory blocks. FPT 2004: 457-460 | |
| c61 | Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Autonomous Memory Block for reconfigurable computing. ISCAS (2) 2004: 581-584 | |
| 2003 | ||
| j7 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Wordlength optimization for linear digital signal processing. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1432-1442 (2003) | |
| j6 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthesis of saturation arithmetic architectures. ACM Trans. Design Autom. Electr. Syst. 8(3): 334-354 (2003) | |
| c60 | Sambuddhi Hettiaratchi, Peter Y. K. Cheung: Mesh Partitioning Approach to Energy Efficient Data Layout. DATE 2003: 11076-11081 | |
| c59 | Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: A Hardware Gaussian Noise Generator for Channel Code Evaluation. FCCM 2003: 69- | |
| c58 | Andrew Royal, Peter Y. K. Cheung: Globally Asynchronous Locally Synchronous FPGA Architectures. FPL 2003: 355-364 | |
| c57 | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. FPL 2003: 396-405 | |
| c56 | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL 2003: 606-615 | |
| c55 | Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: Non-uniform Segmentation for Hardware Function Evaluation. FPL 2003: 796-807 | |
| c54 | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. FPL 2003: 1071-1074 | |
| c53 | Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: Hierarchical segmentation schemes for function evaluation. FPT 2003: 92-99 | |
| c52 | T. K. Lee, Arran Derbyshire, Wayne Luk, Peter Y. K. Cheung: High-level language extensions for run-time reconfigurable systems. FPT 2003: 144-151 | |
| c51 | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Multitasking in hardware-software codesign for reconfigurable computer. ISCAS (5) 2003: 621-624 | |
| c50 | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Architectures for function evaluation on FPGAs. ISCAS (2) 2003: 804-807 | |
| c49 | Theerayod Wiangtong, Chun Te Ewe, Peter Y. K. Cheung: SONICmole: a debugging environment for the UltraSONIC reconfigurable computer. ISCAS (2) 2003: 808-811 | |
| e2 | Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa (Eds.): Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings. Lecture Notes in Computer Science 2778, Springer 2003, isbn 3-540-40822-3 | |
| 2002 | ||
| j5 | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign. Design Autom. for Emb. Sys. 6(4): 425-449 (2002) | |
| c48 | Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke: Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory. DATE 2002: 902-908 | |
| c47 | Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. FCCM 2002: 3-12 | |
| c46 | Jörn Gause, Peter Y. K. Cheung, Wayne Luk: Reconfigurable Shape-Adaptive Template Matching Architectures. FCCM 2002: 98- | |
| c45 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Optimum Wordlength Allocation. FCCM 2002: 219-228 | |
| c44 | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. FCCM 2002: 297-298 | |
| c43 | Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi: Customising Floating-Point Designs. FCCM 2002: 315-317 | |
| c42 | Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang: Automating Customisation of Floating-Point Designs. FPL 2002: 523-533 | |
| c41 | Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung: Run-Time Adaptive Flexible Instruction Processors. FPL 2002: 545-555 | |
| c40 | Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. FPL 2002: 1148-1151 | |
| c39 | Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi: Floating-point bitwidth analysis via automatic differentiation. FPT 2002: 158-165 | |
| c38 | Dong-U Lee, T. K. Lee, Wayne Luk, Peter Y. K. Cheung: Incremental programming for reconfigurable engines. FPT 2002: 411-415 | |
| c37 | Shay Ping Seng, Krishna V. Palem, Rodric M. Rabbah, Weng-Fai Wong, Wayne Luk, Peter Y. K. Cheung: PD-XML: extensible markup language for processor description. FPT 2002: 437-440 | |
| c36 | Henry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen: Strassen's matrix multiplication for customisable processors. FPT 2002: 453-456 | |
| c35 | Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke: Energy efficient address assignment through minimized memory row switching. ICCAD 2002: 577-581 | |
| 2001 | ||
| j4 | Nabeel Shirazi, Dan Benyamin, Wayne Luk, Peter Y. K. Cheung, Shaori Guo: Quantitative Analysis of FPGA-based Database Searching. VLSI Signal Processing 28(1-2): 85-96 (2001) | |
| c34 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Heuristic datapath allocation for multiple wordlength systems. DATE 2001: 791-797 | |
| c33 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: The Multiple Wordlength Paradigm. FCCM 2001: 51-60 | |
| c32 | Jörn Gause, Carsten Reuter, Holger Kropp, Peter Y. K. Cheung, Wayne Luk: The Effect of FPGA Granularity on Video Codec Implementations. FCCM 2001: 287-288 | |
| c31 | Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk: A Digit-Serial Structure for Reconfigurable Multipliers. FPL 2001: 565-573 | |
| c30 | K. T. Tiew, A. J. Payne, Peter Y. K. Cheung: MASH delta-sigma modulators for wideband and multi-standard applications. ISCAS (4) 2001: 778-781 | |
| 2000 | ||
| j3 | Simon D. Haynes, John Stone, Peter Y. K. Cheung, Wayne Luk: Video Image Processing with the Sonic Architecture. IEEE Computer 33(4): 50-57 (2000) | |
| c29 | ||
| c28 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Multiple Precision for Resource Minimization. FCCM 2000: 307-308 | |
| c27 | Jörn Gause, Peter Y. K. Cheung, Wayne Luk: Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. FPL 2000: 96-105 | |
| c26 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Multiple-Wordlength Resource Binding. FPL 2000: 646-655 | |
| 1999 | ||
| c25 | Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung: Reconfigurable Computing for Augmented Reality. FCCM 1999: 136-145 | |
| c24 | Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone: SONIC - A Plug-In Architecture for Video Processing. FCCM 1999: 280-281 | |
| c23 | Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone: SONIC - A Plug-In Architecture for Video Processing. FPL 1999: 21-30 | |
| c22 | Nabeel Shirazi, Wayne Luk, Dan Benyamin, Peter Y. K. Cheung: Quantitative Analysis of Run-Time Reconfigurable Database Search. FPL 1999: 253-263 | |
| c21 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. FPL 1999: 323-332 | |
| 1998 | ||
| c20 | Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung: Automating Production of Run-Time Reconfigurable Designs. FCCM 1998: 147- | |
| c19 | Simon D. Haynes, Peter Y. K. Cheung: A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure. FCCM 1998: 226- | |
| c18 | Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung: Run-Time Management of Dynamically Recongigurable Designs. FPL 1998: 59-68 | |
| 1997 | ||
| j2 | José T. de Sousa, Peter Y. K. Cheung: Diagnosis of Boards for Realistic Interconnect Shorts. J. Electronic Testing 11(2): 157-171 (1997) | |
| c17 | Pedro A. Molina, Peter Y. K. Cheung: A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. ASYNC 1997: 126-139 | |
| c16 | José T. de Sousa, Peter Y. K. Cheung: Improved diagnosis of realistic interconnect shorts. ED&TC 1997: 501-505 | |
| c15 | Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung: Compilation tools for run-time reconfigurable designs. FCCM 1997: 56-65 | |
| c14 | Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Luk, Richard Sandiford: Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. FPL 1997: 91-100 | |
| c13 | Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K. Cheung: Pipeline morphing and virtual pipelines. FPL 1997: 111-120 | |
| c12 | Anjit Sekhar Chaudhuri, Peter Y. K. Cheung, Wayne Luk: A reconfigurable data-localised array for morphological algorithms. FPL 1997: 344-353 | |
| c11 | David S. Bormann, Peter Y. K. Cheung: Asnchronous Wrapper for Heterogeneous Systems. ICCD 1997: 307-314 | |
| e1 | Wayne Luk, Peter Y. K. Cheung, Manfred Glesner (Eds.): Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings. Lecture Notes in Computer Science 1304, Springer 1997, isbn 3-540-63465-7 | |
| 1996 | ||
| j1 | Timo Koskinen, Peter Y. K. Cheung: Hierarchical tolerance analysis using statistical behavioral models. IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 506-516 (1996) | |
| c10 | Nawwaf N. Kharma, Majd Alwan, Peter Y. K. Cheung: An incremental machine learning mechanism applied to robot navigation. ANZIIS 1996: 325-328 | |
| c9 | Majd Alwan, Peter Y. K. Cheung, Akram Saleh, Nour E. Cheikh Obeid: Combining goal-directed, reactive and reflexive navigation in autonomous mobile robots. ANZIIS 1996: 346-349 | |
| c8 | Hasan Demirel, Thomas J. Clarke, Peter Y. K. Cheung: Adaptive Automatic Facial Feature Segmentation. FG 1996: 277-282 | |
| 1994 | ||
| c7 | Salman Ahmed, Peter Y. K. Cheung, Phil Collins: A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation. EDAC-ETC-EUROASIC 1994: 665 | |
| c6 | Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke: Area & Time Limitations of FPGA-based Virtual Hardware. ICCD 1994: 184-189 | |
| c5 | Akachai Sang-In, Peter Y. K. Cheung: A Method of Representative Fault Selection in Digital Circuits for ATPG. ISCAS 1994: 73-76 | |
| c4 | Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke: Virtual Hardware and the Limits of Computational Speed-up. ISCAS 1994: 159-162 | |
| c3 | Salman Ahmed, Peter Y. K. Cheung: Analog Fault Diagnosis - A Practical Approach. ISCAS 1994: 351-354 | |
| 1993 | ||
| c2 | Nasir-ud-Din Gohar, Peter Y. K. Cheung: A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout. ISCAS 1993: 1770-1773 | |
| 1991 | ||
| c1 | Vicente Fuentes-Sánchez, Peter Y. K. Cheung: A Tag Coprocessor Architecture for Symbolic Languages. ICCD 1991: 370-373 | |
Colors in the list of coauthors
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