| 2013 | ||
|---|---|---|
| j4 | Jongwon Lee, Jonghee M. Youn, Doosan Cho, Yunheung Paek: Reducing instruction bit-width for low-power VLIW architectures. ACM Trans. Design Autom. Electr. Syst. 18(2): 25 (2013) | |
| 2012 | ||
| c10 | Jongwon Lee, Doosan Cho, Yunheung Paek: An Efficient Management Technique for Fast SRAM Subsystems. ICHIT (1) 2012: 412-419 | |
| c9 | Jonghee W. Yoon, Kabsu Han, Doosan Cho, Jeonghun Cho: An Efficient Application Mapping for Coarse-Grained Reconfigurable Architectures. ICHIT (1) 2012: 420-427 | |
| c8 | Jonghee M. Youn, Doosan Cho: A Delay and Distance Aware Code Mapping Technique for Coarse-Grained Reconfigurable Array Processors. ICHIT (2) 2012: 488-495 | |
| 2011 | ||
| j3 | Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee W. Yoon, Doosan Cho, Yunheung Paek: High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1599-1609 (2011) | |
| c7 | Jonghee W. Yoon, Jongeun Lee, Jaewan Jung, Sanghyun Park, Yongjoo Kim, Yunheung Paek, Doosan Cho: I2CRF: Incremental interconnect customization for embedded reconfigurable fabrics. DATE 2011: 1346-1351 | |
| c6 | Doosan Cho: A Memory Access Pattern Based Data Distribution Technique for Array Processors. ICHIT (2) 2011: 633-640 | |
| 2009 | ||
| j2 | Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Minwook Ahn, Yunheung Paek: Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 554-567 (2009) | |
| c5 | Minwook Ahn, Jonghee M. Youn, Youngkyu Choi, Doosan Cho, Yunheung Paek: Iterative Algorithm for Compound Instruction Selection with Register Coalescing. DSD 2009: 513-520 | |
| 2008 | ||
| c4 | Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil Dutt, Yunheung Paek, SunJun Ko: Compiler driven data layout optimization for regular/irregular array access patterns. LCTES 2008: 41-50 | |
| 2007 | ||
| j1 | Yunheung Paek, Minwook Ahn, Doosan Cho, Taehwan Kim: Efficient embedded code generation with multiple load/store instructions. Softw., Pract. Exper. 37(11): 1133-1159 (2007) | |
| c3 | Doosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek: Software controlled memory layout reorganization for irregular array access patterns. CASES 2007: 179-188 | |
| c2 | Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek: Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors. CC 2007: 16-31 | |
| 2006 | ||
| c1 | Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek: Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs. EUC Workshops 2006: 741-754 | |
Data released under the ODC-BY 1.0 license — See also our legal information page