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 | 2013 | |
|---|---|---|
| j13 |      | KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho: A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier. J. Solid-State Circuits 48(4): 1009-1017 (2013) |
| j12 | | Wonsik Yu, Jaewook Kim, KwangSeok Kim, SeongHwan Cho: A Time-Domain High-Order MASH $\Delta\Sigma$ ADC Using Voltage-Controlled Gated-Ring Oscillator. IEEE Trans. on Circuits and Systems 60-I(4): 856-866 (2013) |
| c18 | | Antonio Liscidini, SeongHwan Cho, Tony Chan Carusone, Tanay Karnik, Mike Keaveney, Brian Otis, Aaron Partridge, Christoph Sandner: F5: Frequency generation and clock distribution. ISSCC 2013: 508-509 |
| 2012 | ||
| j11 | | Jaewon Lee, Woojae Lee, SeongHwan Cho: A High-Frequency Compensated Crosstalk and ISI Equalizer for Multi-Channel On-Chip Interconnect in 130-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 314-321 (2012) |
| j10 | | Pyoungwon Park, Dongmin Park, SeongHwan Cho: A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL. J. Solid-State Circuits 47(10): 2433-2443 (2012) |
| j9 | | Junghyup Lee, SeongHwan Cho: A 1.4-µW 24.9-ppm/°C Current Reference With Process-Insensitive Temperature Compensation in 0.18-µm CMOS. J. Solid-State Circuits 47(10): 2527-2533 (2012) |
| j8 | | Dongmin Park, SeongHwan Cho: A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 μ m CMOS. J. Solid-State Circuits 47(12): 2989-2998 (2012) |
| j7 | | Jaewon Lee, Woojae Lee, SeongHwan Cho: A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS. IEEE Trans. on Circuits and Systems 59-I(1): 124-136 (2012) |
| j6 | | Tae-Kwang Jang, Jaewook Kim, Young-Gyu Yoon, SeongHwan Cho: A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase Interpolator and Digital Calibration. IEEE Trans. VLSI Syst. 20(8): 1368-1372 (2012) |
| c17 | | Ken Chang, SeongHwan Cho: Session 19 overview: 20+ Gb/s wireline transceivers and injection-locked clocking: Wireline subcommittee. ISSCC 2012: 322-323 |
| c16 | | Pyoungwon Park, Jaejin Park, Hojin Park, SeongHwan Cho: An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS. ISSCC 2012: 336-337 |
| c15 | | Dongmin Park, SeongHwan Cho: A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS. ISSCC 2012: 344-346 |
| c14 | | Ichiro Fujimori, SeongHwan Cho, Joshua Friedrich, John Stonick: Optical PCB interconnects, Niche or mainstream? ISSCC 2012: 516 |
| 2011 | ||
| j5 | | Joonhee Lee, Sunghyun Park, SeongHwan Cho: A 470-µW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme. IEEE Trans. VLSI Syst. 19(1): 61-70 (2011) |
| c13 | | Pyoungwon Park, Dongmin Park, SeongHwan Cho: A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL. CICC 2011: 1-4 |
| c12 | | Jaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho: A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS. ISSCC 2011: 176-178 |
| 2010 | ||
| j4 | | Sung-Jin Kim, Min-Chang Cho, SeongHwan Cho: An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder. IEICE Transactions 93-C(6): 785-795 (2010) |
| j3 | | Jaewook Kim, Tae-Kwang Jang, Young-Gyu Yoon, SeongHwan Cho: Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter. IEEE Trans. on Circuits and Systems 57-I(1): 18-30 (2010) |
| c11 | | Woojae Lee, SeongHwan Cho: A 2.4-GHz reference doubled fractional-N PLL with dual phase detector in 0.13-μm CMOS. ISCAS 2010: 1328-1331 |
| c10 | | Sung-Pah Lee, SeongHwan Cho: A background KDCO compensation technique for constant bandwidth in all-digital phase-locked loop. ISCAS 2010: 3401-3404 |
| c9 | | Young-Hwa Kim, Jaewon Lee, SeongHwan Cho: A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages. ISCAS 2010: 4041-4044 |
| 2009 | ||
| j2 | | Joonhee Lee, Sungjun Kim, Sehyung Jeon, Woojae Lee, SeongHwan Cho: A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS. IEICE Transactions 92-C(4): 589-591 (2009) |
| c8 | | Sunghyun Park, Changwook Min, SeongHwan Cho: A 95nW Ring Oscillator-based Temperature Sensor for RFID Tags in 0.13µm CMOS. ISCAS 2009: 1153-1156 |
| c7 | | Min-Chang Cho, Jee-Yeon Kim, SeongHwan Cho: A Bio-impedance Measurement System for Portable Monitoring of Heart Rate and Pulse Wave Velocity using Small Body Area. ISCAS 2009: 3106-3109 |
| 2008 | ||
| j1 | | Young-Gyu Yoon, Jaewook Kim, Tae-Kwang Jang, SeongHwan Cho: A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators. IEEE Trans. on Circuits and Systems 55-I(11): 3571-3581 (2008) |
| c6 | | Sung-Jin Kim, Min-Chang Cho, Joonhyun Park, Kisuk Song, Yul Kim, SeongHwan Cho: An ultra low power UHF RFID tag front-end for EPCglobal Gen2 with novel clock-free decoder. ISCAS 2008: 660-663 |
| 2006 | ||
| c5 | | Jaewook Kim, SeongHwan Cho: A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator. ISCAS 2006 |
| c4 | | Dongmin Park, SeongHwan Cho: A power-optimized CMOS LC VCO with wide tuning range in 0.5-V supply. ISCAS 2006 |
| c3 | | Jaewon Lee, SeongHwan Cho: A Low Power Transmitter for Phase-Shift Keying Modulation Schemes. PIMRC 2006: 1-5 |
| 2005 | ||
| c2 | | SeongHwan Cho, Kee-Eung Kim: Variable bandwidth allocation scheme for energy efficient wireless sensor network. ICC 2005: 3314-3318 |
| c1 | | SeongHwan Cho, Sungmin Ock, Sang-Hoon Lee, Joonsuk Lee: A low power pipelined analog-to-digital converter using series sampling capacitors. ISCAS (6) 2005: 6178-6181 |
Colors in the list of coauthors
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