Kiyoung Choi

Kiyoung Choi, Sungup Jo, Hwamin Lee, Changsung Jeong: CPU-based speed acceleration techniques for shear warp volume rendering. Multimedia Tools Appl. 64(2): 309-329 (2013)

Junwhan Ahn, Kiyoung Choi: Isomorphism-Aware Identification of Custom Instructions With I/O Serialization. IEEE Trans. on CAD of Integrated Circuits and Systems 32(1): 34-46 (2013)

Jinho Lee, Dongwook Lee, Sunwook Kim, Kiyoung Choi: Deflection routing in 3D Network-on-Chip with TSV serialization. ASP-DAC 2013: 29-34

Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi: Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches. ASP-DAC 2013: 285-290

Kyuseung Han, Kiyoung Choi, Jongeun Lee: Compiling control-intensive loops for CGRAs with state-based full predication. DATE 2013: 1579-1582

Kiyoung Choi, John Kim, Gabriel Loh: Guest Editorial New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 121-123 (2012)

John Kim, Kiyoung Choi, Gabriel Loh: Exploiting New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 124-136 (2012)

Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang: ESL Design Methodology. J. Electrical and Computer Engineering 2012 (2012)

Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi: Active Memory Processor for Network-on-Chip-Based Architecture. IEEE Trans. Computers 61(5): 622-635 (2012)

Jinho Lee, Kiyoung Choi: Memory-aware mapping and scheduling of tasks and communications on many-core SoC. ASP-DAC 2012: 419-424

Kyuseung Han, Seongsik Park, Kiyoung Choi: State-based full predication for low power coarse-grained reconfigurable architecture. DATE 2012: 1367-1372

Junwhan Ahn, Kiyoung Choi: Lower-bits cache for low power STT-RAM caches. ISCAS 2012: 480-483

Mingyang Zhu, Jinho Lee, Kiyoung Choi: An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth. VLSI-SoC 2012: 18-23

Ganghee Lee, Kiyoung Choi, Nikil D. Dutt: Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 30(5): 637-650 (2011)

Junwhan Ahn, Imyong Lee, Kiyoung Choi: A polynomial-time custom instruction identification algorithm based on dynamic programming. ASP-DAC 2011: 573-578

Junwhan Ahn, Kiyoung Choi: An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors. CODES+ISSS 2011: 345-354

Hyunjik Song, Kiyoung Choi: Simulated annealing-based diffusive load balancing on many-core SoC. ICAC 2011: 187-188

Seokhyun Lee, Kiyoung Choi: High-level synthesis with distributed controller for fast timing closure. ICCAD 2011: 193-199

Jong Kyung Paek, Jong-eun Lee, Kiyoung Choi: CRM: Configurable Range Memory for Fast Reconfigurable Computing. IPDPS Workshops 2011: 158-165

Jae Hong Park, Kiyoung Choi, Dong-Yeon Lee, Jaesool Shim, Tae Song Kim: Resonant properties of piezoelectric cantilever transducers fabricated on the SiC membrane. NEMS 2011: 61-63

Ganghee Lee, Yongjin Ahn, Seokhyun Lee, Jeongki Son, Kiwook Yoon, Kiyoung Choi: Communication architecture design for reconfigurable multimedia SoC platform. Design Autom. for Emb. Sys. 14(1): 1-20 (2010)

Jong Kyung Paek, Kiyoung Choi, Jong-eun Lee: Binary acceleration using coarse-grained reconfigurable architecture. SIGARCH Computer Architecture News 38(4): 33-39 (2010)

Yoonjin Kim, Rabi N. Mahapatra, Kiyoung Choi: Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture. IEEE Trans. VLSI Syst. 18(10): 1471-1482 (2010)

Ganghee Lee, Kiyoung Choi: Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture. AHS 2010: 265-272

Ganghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil D. Dutt: Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. ARC 2010: 231-243

Kyungwook Chang, Kiyoung Choi: Memory-Centric Communication Architecture for Reconfigurable Computing. ARC 2010: 400-405

Kyuseung Han, Jong Kyung Paek, Kiyoung Choi: Acceleration of control flow on CGRA using advanced predicated execution. FPT 2010: 429-432

Ganghee Lee, Kyungwook Chang, Kiyoung Choi: Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution. IPDPS Workshops 2010: 1-4

Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, Kiyoung Choi: Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture. IEEE Trans. VLSI Syst. 17(5): 593-603 (2009)

Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi: Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus. IEEE Trans. VLSI Syst. 17(8): 1034-1047 (2009)

Youngchul Cho, Kiyoung Choi: Code decomposition and recomposition for enhancing embedded software performance. ASP-DAC 2009: 624-629

Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi: Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency. DAC 2009: 806-811

Manhwee Jo, Ganghee Lee, Kyungwook Chang, Kyuseung Han, Kiyoung Choi, Hoonmo Yang, Kiwook Yoon: Coarse-grained reconfigurable architecture for multiple application domains: a case study. ICHIT 2009: 546-553

Jong-eun Lee, Kiyoung Choi, Nikil Dutt: Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures. IJES 3(3): 119-127 (2008)

Soonhoi Ha, Kiyoung Choi, Taewhan Kim, Krisztián Flautner, Sang Lyul Min, Wang Yi: Introduction to embedded systems week 2006 special issue. ACM Trans. Embedded Comput. Syst. 7(2) (2008)

Yongjin Ahn, Keesung Han, Ganghee Lee, Hyunjik Song, Jun-hee Yoo, Kiyoung Choi, Xingguang Feng: SoCDAL: System-on-chip design AcceLerator. ACM Trans. Design Autom. Electr. Syst. 13(1) (2008)

Dongwook Lee, Sungjoo Yoo, Kiyoung Choi: Entry control in network-on-chip for memory power reduction. ISLPED 2008: 171-176

V. K. Prasad Arava, Manhwee Jo, HyoukJoong Lee, Kiyoung Choi: A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines. ISVLSI 2008: 197-202

Youngchul Cho, Nacer-Eddine Zergainoh, Sungjoo Yoo, Ahmed Amine Jerraya, Kiyoung Choi: Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip. Design Autom. for Emb. Sys. 11(2-3): 167-191 (2007)

Jinyong Jung, Sungjoo Yoo, Kiyoung Choi: Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction. Design Autom. for Emb. Sys. 11(4): 223-247 (2007)

Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Instruction set synthesis with efficient instruction encoding for configurable processors. ACM Trans. Design Autom. Electr. Syst. 12(1) (2007)

Imyong Lee, Dongwook Lee, Kiyoung Choi: Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation. ASAP 2007: 383-390

Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi: Communication Architecture Synthesis of Cascaded Bus Matrix. ASP-DAC 2007: 171-177

Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya: Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes. IEEE International Workshop on Rapid System Prototyping 2007: 195-201

Youngchul Cho, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi: Buffer Size Reduction through Control-Flow Decomposition. RTCSA 2007: 183-190

Ganghee Lee, Seokhyun Lee, Yongjin Ahn, Kiyoung Choi: Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration. ICSAMOS 2007: 50-57

Manhwee Jo, V. K. Prasad Arava, Hoonmo Yang, Kiyoung Choi: Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture. SoCC 2007: 127-130

Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich (Eds.): Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007. ACM 2007, isbn 978-1-59593-824-4

Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi: Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization. CoRR abs/0710.4704 (2007)

Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi: Worst case execution time analysis for synthesized hardware. ASP-DAC 2006: 905-910

Minwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonjin Kim, Mary Kiemb, Kiyoung Choi: A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. DATE 2006: 363-368

Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek: Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. ISLPED 2006: 310-315

Reinaldo A. Bergamaschi, Kiyoung Choi (Eds.): Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006. ACM 2006, isbn 1-59593-370-0

Daehong Kim, Dongwan Shin, Kiyoung Choi: Pipelining with common operands for power-efficient linear systems. IEEE Trans. VLSI Syst. 13(9): 1023-1034 (2005)

Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya: Scheduler implementation in MP SoC design. ASP-DAC 2005: 151-156

Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi: Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization. DATE 2005: 12-17

Mary Kiemb, Kiyoung Choi: Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems. CASES 2004: 230-237

Whee Kuk Kim, Kiyoung Choi, Byung-Ju Yi: A Mobility Analysis Method of Closed-chain Mechanisms with Over-constraints and Non-holonomic Constraints. ICRA 2004: 2801-2807

Mary Kiemb, Kiyoung Choi: Application-specific configuration of multithreaded processor architecture for embedded applications. ISCAS (2) 2004: 941-944

Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy (Eds.): Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004. ACM 2004

Nikil D. Dutt, Kiyoung Choi: Configurable Processors for Embedded Computing. IEEE Computer 36(1): 120-123 (2003)

Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, Soo-Ik Chae: An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design. Design Autom. for Emb. Sys. 8(2-3): 119-138 (2003)

Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Compilation Approach for Coarse-Grained Reconfigurable Architectures. IEEE Design & Test of Computers 20(1): 26-33 (2003)

Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. ASAP 2003: 172-182

Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh: Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. DATE 2003: 20132-20137

Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Energy-efficient instruction set synthesis for application-specific processors. ISLPED 2003: 330-333

Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: An algorithm for mapping loops onto coarse-grained reconfigurable architectures. LCTES 2003: 183-188

Sunghyun Lee, Sungjoo Yoo, Kiyoung Choi: Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model. CODES 2002: 199-204

Jong-eun Lee, Kiyoung Choi, Nikil Dutt: Efficient instruction encoding for automatic instruction set design of configurable ASIPs. ICCAD 2002: 649-654

Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo: An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. ISLPED 2002: 84-87

Sanghun Park, Kiyoung Choi: Performance-driven high-level synthesis with bit-level chaining andclock selection. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 199-212 (2001)

Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi: Partial bus-invert coding for power optimization of application-specific systems. IEEE Trans. VLSI Syst. 9(2): 377-383 (2001)

Youngsoo Shin, Kiyoung Choi, Young-Hoon Chang: Narrow bus encoding for low-power DSP systems. IEEE Trans. VLSI Syst. 9(5): 656-660 (2001)

Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi: High-level synthesis under multi-cycle interconnect delay. ASP-DAC 2001: 662

Kyoungseok Rha, Kiyoung Choi: Area-efficient buffer binding based on a novel two-port FIFO structure. CODES 2001: 122-127

Sungtaek Lim, Jihong Kim, Kiyoung Choi: Scheduling-based code size reduction in processors with indirect addressing mode. CODES 2001: 165-169

Jinyong Jung, Sungjoo Yoo, Kiyoung Choi: Performance improvement of multi-processor systems cosimulation based on SW analysis. DATE 2001: 749-753

Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi: Behavior-to-Placed RTL Synthesis with Performance-Driven Placement. ICCAD 2001: 320-

Daehong Kim, Dongwan Shin, Kiyoung Choi: Low power pipelining of linear systems: a common operand centric approach. ISLPED 2001: 225-230

Sungjoo Yoo, Kiyoung Choi: Optimizing Timed Cosimulation by Hybrid Synchronization. Design Autom. for Emb. Sys. 5(2): 129-152 (2000)

Sungjoo Yoo, Kiyoung Choi, Dong Sam Ha: Performance improvement of geographically distributed cosimulation by hierarchically grouped messages. IEEE Trans. VLSI Syst. 8(5): 492-502 (2000)

Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi: Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. ASP-DAC 2000: 169-174

Youngsoo Shin, Kiyoung Choi: Narrow bus encoding for low power systems. ASP-DAC 2000: 217-220

Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, Kiyoung Choi: Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model. CODES 2000: 77-81

Youngsoo Shin, Daehong Kim, Kiyoung Choi: Schedulability-driven performance analysis of multiple mode embedded real-time systems. DAC 2000: 495-500

Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi: Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. DATE 2000: 663-668

Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai: Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. ICCAD 2000: 365-368

Junghwan Choi, Jinhwan Jeon, Kiyoung Choi: Power minimization of functional units partially guarded computation. ISLPED 2000: 131-136

Jae-Hee Won, Kiyoung Choi: Low power self-timed Radix-2 division (poster session). ISLPED 2000: 210-212

Sungjoo Yoo, Kiyoung Choi: Optimizing geographically distributed timed cosimulation by hierarchically grouped messages. CODES 1999: 100-104

Youngsoo Shin, Kiyoung Choi: Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems. DAC 1999: 134-139

Sanghun Park, Kiyoung Choi: Performance-Driven Scheduling with Bit-Level Chaining. DAC 1999: 286-291

Byungil Jeong, Sungjoo Yoo, Kiyoung Choi: Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design. FPGA 1999: 247

Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Kiyoung Choi: An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping. Design Autom. for Emb. Sys. 3(2-3): 163-186 (1998)

Jinhwan Jeon, Kiyoung Choi: Loop Pipelining in Hardware-Software Partitioning. ASP-DAC 1998: 361-366

Sungjoo Yoo, Kiyoung Choi: Optimistic distributed timed cosimulation based on thread simulation model. CODES 1998: 71-75

Youngsoo Shin, Kiyoung Choi: Rate Assignment for Embedded Reactive Real-Time Systems. EUROMICRO 1998: 10237-

Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi: Partial bus-invert coding for power optimization of system level bus. ISLPED 1998: 127-129

Youngsoo Shin, Kiyoung Choi: Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign. CODES 1997: 3-8

Daehong Kim, Kiyoung Choi: Power-conscious High Level Synthesis Using Loop Folding. DAC 1997: 441-445

Dongwan Shin, Kiyoung Choi: Low power high level synthesis by increasing data correlation. ISLPED 1997: 62-67

KiJong Lee, Kiyoung Choi: Self-timed divider based on RSD number system. IEEE Trans. VLSI Syst. 4(2): 292-295 (1996)

Youngsoo Shin, Kiyoung Choi: Software synthesis through task decomposition by dependency analysis. ICCAD 1996: 98-104

Sungjoo Yoo, Jinhwan Jeon, Seongsoo Hong, Kiyoung Choi: Hardware-Software Codesign of Resource-Constrained Real-Time Systems. RTCSA 1996: 286-

Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha: An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. ASP-DAC 1995

Yongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jae-Hee Won, Kiyoung Choi: Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification. ISCAS 1995: 924-927

Kiyoung Choi, KiJong Lee, Jun-Woo Kang: A Self-Timed Divider Using RSD Number System. ICCD 1994: 504-507

Sun Young Hwang, Tom Blank, Kiyoung Choi: Fast functional simulation: an incremental approach. IEEE Trans. on CAD of Integrated Circuits and Systems 7(7): 765-774 (1988)

Kiyoung Choi, Sun Young Hwang, Tom Blank: Incremental-in-time Algorithm for Digital Simulation. DAC 1988: 501-505